參數(shù)資料
型號: CYNCP80192
英文描述: Network Processing
中文描述: 網(wǎng)絡(luò)處理
文件頁數(shù): 32/42頁
文件大?。?/td> 679K
代理商: CYNCP80192
CYNCP80192
Document #: 38-02043 Rev. *B
Page 32 of 42
Table 16-5. AC Timing Parameters for ZBT and Flow-Through SSRAM
Parameter
T
CLK
T
CKHI
T
CKLO
T
SA
T
HA
T
CKOV
T
CLK2
T
CLKPHSL
T
CKSE
T
SCK
T
CKSD
T
CKOLZ
T
CKOHZ
Description
Test Conditions
Load (pF)
CYNPC80192–83
Min
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
50
CLK period: max frequency
CLK high pulse; worst-case 40%–60% duty cycle
CLK low pulse; worst-case 40%–60% duty cycle
Address setup time to CLK rising edge
Address hold time to CLK rising edge
Clock to output valid (network processor interface)
Clock to CLK2X delay
Clock to PHS_L delay
Clock to output valid (NSE Interface)
Clock to SCLK delay
Clock to output valid (SDATA)
Clock to output in low-Z
Clock to output in high-Z
8
8
6
2
30
18
4
7
12
6
13
40
20
3
7
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