參數(shù)資料
型號(hào)： CYNCP80192
英文描述： Network Processing
中文描述： 網(wǎng)絡(luò)處理
文件頁(yè)數(shù)： 24/42頁(yè)
文件大?。?/td> 679K
代理商： CYNCP80192
CYNCP80192
Document #: 38-02043 Rev. *B
Page 24 of 42
9.0
ZBT Pipelined SSRAM Interface Mode
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data
is sampled two cycles later; for Read cycles, the data is available to the processor two cycles later. Both Write- and Read-cycle
latency is two cycles and there is no gap required between Read and Write operations. Every cycle is available for the network
processor(s) for full utilization of the bus bandwidth. See
Figure 9-1
.
Note
. BWE_L is not used in this mode and should be tied
inactive.
CLK
ADR[9:0]
BW_L[7:0]
DATA[63:0]
CE_L
CE_2
R/W_L
STRB
CPID[7:0]
1
2
3
4
5
6
7
A1
A2
A3
A4
A5
A6
D1
Q2
D3
D4
Q5
CPID
Write
Read
Write
Write
Read
Read
Figure 9-1. ZBT Pipelined SRAM Interface (Mode 000)
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CYNPC80192-BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Database Coprocessor
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