參數(shù)資料
型號(hào)： CYNCP80192
英文描述： Network Processing
中文描述： 網(wǎng)絡(luò)處理
文件頁(yè)數(shù)： 13/42頁(yè)
文件大?。?/td> 679K
代理商： CYNCP80192
CYNCP80192
Document #: 38-02043 Rev. *B
Page 13 of 42
SSRAM Present
. This field informs the coprocessor whether the associative data SSRAM is connected to the NSE (bit is set to
1; see
Figure 13-1
) or connected to the network processor SRAM interface (bit is set to 0; see
Figure 13-2
).
INTR_Polarity
. This bit controls the polarity of the INTR/INTR_L signal. When this signal is high, the INTR/INTR_L signal is active
high. When this signal is low, the INTR/INTR_L signal is active low.
Search Result Bit in Data Field
. If this bit is set to 1, the Hit or Miss information will be attached to the associative data field in
bit 63. This bit has significance only when associative SSRAM is present (see Result Register 1 for the Search command). This
bit does not replace the hit bit located in Result Register 0.
External Transceiver Present
. If an external transceiver is used to drive several NSE devices, this bit should be set to 1.
6.2.2
The error and status register is 64 bits wide.
Table 6-4
shows the bit positions of the error status register. The errors shown in
Table 6-5
will be detected by the NDC and the corresponding error bit will be set in the error and status register. Once it is Read,
the error and status register will be cleared.
Error Bits
. The error bits field holds the type of error. In the case of multiple errors, multiple error bits may be set. The context
descriptor index will contain the index where the last error occurred. When an error occurs, the error bit is set along with the done
bit in Result Register 0. The class and type of error (soft error [SE] or hard error [HE]) are indicated in the error and status register.
When an error occurs, the INTR signal is asserted and a corresponding error bit is set along with the context descriptor index to
identify the erroneous command. The interrupt signal is programmable as active low or active high depending upon the system
requirement. See the description of the CFG register for further detail.
Error and Status Register
Context Descriptor Index
. This field identifies the context descriptor that caused the last error condition. In the case of multiple
errors, this field will be overwritten.
DESC_AFULL
. This bit indicates that the descriptor array is almost full. When this flag is set, the processor(s) can send only two
more commands to the descriptors. The DESC_AF flag will be cleared if more that two descriptors are available.
DESC_FULL
. This bit indicates that the descriptor array is full. When this flag is set, the processor can send no commands to
the descriptor. The DESC_FULL flag is cleared upon Reading the status register.
SE_FULL
.
[8]
This bit indicates that the table in the NSE is full.
SE
. The SE bit indicates that the error is recoverable and that the command has to be reissued.
HE
. The HE bit indicates that the error is not recoverable, and that the coprocessor has to be reset and reinitialized by the software
before further operations are attempted.
6.2.3
The mask register is 64 bits wide. The bits in this field can be used to mask the INTR generated by any of the bits set in the error
and status register. Setting the bits in this register causes the interrupt to be masked. The default value in the mask register is
FFFFFFFF (lower 32 bits only).
Mask Register
Note:
8.
SE_FULL may be altered as a result of executing a Learn or Write command by the NSE. This flag will be cleared upon reading the status register.
Table 6-4. Error and Status Register
63–32
Reserved
31
HE
30
SE
29
28
27
26–13
Reserved
12–8
7–0
SE_FULL
DESC_FULL
DESC_AFULL
Context Desc Index
Error Bits
Table 6-5. Error Codes
Error Bit
0
1
2
3
4
5
6
7
Error Description
Invalid Command (SE)
Reserved
Reserved
Search or Learn size invalid (i.e., 11 in search size field is not allowed) (SE)
NSE access time out (HE)
Reserved
Reserved
Reserved
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