
CYNCP80192
Document #: 38-02043 Rev. *B
Page 3 of 42
LIST OF FIGURES
Figure 2-1. CYNCP80192 Block Diagram ...............................................................................................6
Figure 5-1. NDC Clocks.........................................................................................................................11
Figure 9-1. ZBT Pipelined SRAM Interface (Mode 000)........................................................................24
Figure 10-1. ZBT Flowthrough SSRAM Interface (Mode 001)...............................................................25
Figure 11-1. SyncBurst Pipelined SSRAM Interface (Early Write) ........................................................26
Figure 12-1. SyncBurst Pipelined SSRAM Interface (Late Write)..........................................................27
Figure 13-1. Configuration 1—Associative SSRAM Mode ....................................................................28
Figure 13-2. Configuration 2—Index Mode............................................................................................28
Figure 13-3. Switching Systems Block Diagram....................................................................................28
Figure 14-1. Use of Transceiver Enables ..............................................................................................29
Figure 14-2. Transceiver Connected Between CYNPC80192 and CYNSE70XXX Devices .................29
Figure 16-1. Pinout Diagram..................................................................................................................33
Figure 18-1. Package Bottom View .......................................................................................................40
Figure 18-2. Package Side View ...........................................................................................................40
Figure 18-3. Package Top View ............................................................................................................41