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參數(shù)資料
| 型號： | CYNCP80192 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 23/42頁 |
| 文件大小： | 679K |
| 代理商： | CYNCP80192 |
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CYNCP80192
Document #: 38-02043 Rev. *B
Page 23 of 42
8.0
NDC Subsystem Power-up Initialization Procedure
On power-up (boot), the network processor will apply the following sequence of operations.
1. Write SRST and CFG information to 1 in the CFG register.
2. Wait at least 32 cycles, then poll on SRST.
3. Write the CFG registers to each of the NSEs, starting with the one residing at the least significant address.
4. Write the CFG registers of the last NSE in the depth-cascaded system, setting the LDEV and LRAM bits to a 1.
5. The descriptor block is now Ready for use by the network processor(s) for building, managing, and/or searching the database.
Hardware Interface Timing Protocols—NDC Interface
. The network processor interface of the NDC supports a variety of
SSRAM interfaces. It supports both SyncBurst as well as ZBT SSRAMs. IFC_CFG[2:0] pins select the interface type for the device
as follows. (Refer to SSRAM specifications and application notes from such vendors as IDT and Micron.)
000: ZBT pipelined mode
001: ZBT flowthrough mode
010: SyncBurst pipelined mode (early Write)
011: SyncBurst pipelined mode (late Write)
100–111: Reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYNPC80192-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Database Coprocessor |
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| CYNSE10128-083FGCI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
| CYNSE10128-100FGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
| CYNSE10128-133FGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
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