Master Bus Operation
3-26
ColdFire2/2M User’s Manual
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MOTOROLA
The status register of the ColdFire2/2M, described in
Section 1.4.3.1 Status Register (SR)
,
contains an interrupt priority mask (
IPLB
[2:o]). The value in the interrupt mask is the highest
priority level that the ColdFire2/2M ignores. When an interrupt request has a priority higher
than the value in the mask, the ColdFire2/2M makes the request a pending interrupt.
IPLB
[2:0] must maintain the interrupt request level until the ColdFire2/2M acknowledges the
interrupt to guarantee that the interrupt is recognized. The ColdFire2/2M continuously
samples IPLB[2:0] on consecutive rising edges of
CLK
. As a result, the IPLB[2:0] signals are
synchronous and must meet setup and hold times to CLK. If the external IPLB[2:0] signals
are asynchronous, flip-flops should be used to synchronize them before they drive the
IPLB[2:0] signals on the ColdFire2/2M.
The ColdFire2/2M takes an interrupt exception for a pending interrupt within one instruction
boundary after processing any other pending exception with a higher priority. Thus, the
ColdFire2/2M executes at least one instruction in an interrupt exception handler before
recognizing another interrupt request. The following paragraphs describe the two kinds of
interrupt acknowledge bus cycles that can be executed as part of interrupt exception
processing.
3.7.1 Interrupt Acknowledge Bus Cycle (Terminated Normally)
When the ColdFire2/2M processes an interrupt exception, it performs an interrupt
acknowledge bus cycle to obtain the vector number that contains the starting location of the
interrupt exception handler. Most interrupting devices have programmable vector registers
that contain the interrupt vectors for the exception handlers they use. Others may have fixed
vector numbers. The values driven on
MADDR
[31:0],
MTT
[1:0], and
MTM
[2:0] are
dependent on the interrupt acknowledge mode. The interrupt acknowledge mode is
statically determined by the connection of the 68K interrupt acknowledge mode enable
(
IACK_68K
) signal.
The interrupt acknowledge bus cycle is a read transfer. If the ColdFire2/2M is in the ColdFire
interrupt acknowledge mode (IACK_68K negated), it differs from a normal read cycle in the
following respects:
1.
MTT
[1:0]= $3 to indicate a acknowledge/CPU space bus cycle.
2. Address signals
MADDR
[31:5] are set to all ones ($3FFFFFF). The MADDR[4:2]
signals are set to the pending interrupt number, and the MADDR[1:0] signals are
driven low.
3.
MTM
[2:0] are set to the interrupt request level, the inverted values of
IPLB
[2:0]. This
will be nonzero for all interrupt acknowledge cycles.
If the ColdFire2/2M is in the 68K interrupt acknowledge mode (IACK_68K asserted), it differs
in the following respects:
1.
MTT
[1:0] = $0 to indicate a Acknowledge/CPU space bus cycle.
2. Address signals
MADDR
[31:4] are set to all ones ($7FFFFFF). The MADDR[3:1]
signals are set to the pending interrupt number, and the MADDR[0] signal is driven
high.
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.