MOTOROLA
ColdFire2/2M User’s Manual
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xix
LIST OF ILLUSTRATIONS
Figure
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Title
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
4-1
4-2
5-1
5-2
5-3
5-4
5-5
FlexCore Integrated Processor Typical Die Layout...........................................1-3
Design System Overview..................................................................................1-7
ColdFire2/2M System Diagram.........................................................................1-8
ColdFire2/2M Block Diagram..........................................................................1-10
Integer Unit User Programming Model............................................................1-12
Condition Code Register (CCR)......................................................................1-13
MAC Unit User Programming Model...............................................................1-13
Supervisor Programming Model......................................................................1-14
Status Register (SR).......................................................................................1-15
Organization of Integer Data Formats in Data Registers................................1-16
Organization of Integer Data Formats in Address Registers...........................1-17
Memory Operand Addressing.........................................................................1-18
ColdFire2/2M Detailed Block Diagram..............................................................2-1
Byte, Word, and Longword Read Transfer Flowchart.......................................3-7
Normal Transfer (without Wait States)..............................................................3-8
Byte, Word, and Longword Write Transfer Flowchart.......................................3-9
Normal Write Transfer (with wait states).........................................................3-10
Line Read Transfer Flowchart.........................................................................3-12
Line Read Transfer (without wait states).........................................................3-13
Line Write Transfer Flowchart.........................................................................3-15
Line Write Transfer (without wait states).........................................................3-16
Line Write Transfer (with wait states)..............................................................3-17
Example of a Misaligned
Longword
Transfer................................................3-18
Example of a Misaligned Word Transfer.........................................................3-18
Misaligned Word Read Transfer .....................................................................3-19
Example Master Bus Wait State .....................................................................3-21
Interrupt Acknowledge Bus Cycle Flowchart...................................................3-23
ColdFire Mode Interrupt Acknowledge Bus Cycle...........................................3-24
68K Mode Interrupt Acknowledge Bus Cycle..................................................3-26
Bus Exception Cycle.......................................................................................3-29
Initial Power-On Reset....................................................................................3-30
Exception Processing Flowchart.......................................................................4-2
Exception Stack Frame Form............................................................................4-3
Example 8 Kbyte Instruction Cache Interface Diagram ....................................5-2
Cache Control Register (CACR).......................................................................5-6
Access Control Register (ACR0, ACR1)...........................................................5-9
Example 8 Kbyte ROM Interface Diagram......................................................5-11
ROM Base Address Register (ROMBAR0).....................................................5-12
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