
Signal Summary
2-4
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
2.2.4 Master Freeze (MFRZB)
This active-low output signal indicates that the core has been halted. MFRZB is not part of
the M-Bus protocol. It is simply a signal that can be used to alert timers or other peripheral
modules that the core has been halted.
2.2.5 Master Kill (MKILLB)
This active-low output signal qualifies MTSB (i.e. it can assert in other cycles but is only
significant in a cycle where MSTB is asserted). When MKILLB is asserted simultaneously
with MTSB assertion, this indicates a hit in a K-Bus memory and that the external cycle must
be inhibited. This means the current master bus transaction is no longer required and should
be ignored (MTAB should not be asserted). MKILLB is asserted late in the MTSB cycle. Note
that if there is no K-Bus resident memory (ICACHE, SRAM, or ROM), MKILLB never
asserts. See
Table 2-2
for MTSB/MKILLB interaction in table format.
2.2.6 Master Read Data Bus (MRDATA[31:0])
These input signals provide the read data path between the system and the ColdFire2/2M.
The read data bus is 32-bits wide and can transfer 8, 16 or 32 bits of data per bus transfer.
During a line transfer, the data bus is time-multiplexed across multiple clock cycles to
transfer 128 bits.
2.2.7 Master Read Data Input Enable (MIE)
This active-high input signal enables the capturing of MRDATA[31:0]. Power consumption
can be reduced by minimizing signal switching in the ColdFire2/2M by negating MIE when
MRDATA[31:0] is invalid. MIE must be asserted during all functional operation with one
master and during K-Bus memory testing.
2.2.8 Master Read/Write (MRWB)
This output signal indicates the direction of the data transfer for the current bus cycle. A high
level indicates a read cycle and a low level indicates a write cycle.
2.2.9 Master Reset (MRSTB)
This active-low input signal instructs all master bus modules, including the ColdFire2/2M, to
enter reset mode. The ColdFire2/2M will then initiate a reset exception.
2.2.10 Master Size (MSIZ[1:0])
These output signals indicate the data size for the bus transfer. Refer to
Table 2-3
for the
bus size encoding.
Table 2-2. M-Bus Protocol with respect to MTSB and MKILLB
MTSB
0
0
1
MKILLB
1
0
X
M-BUS PROTOCOL
Initiate M-Bus transfer
Nop
Nop
F
Freescale Semiconductor, Inc.
n
.