參數(shù)資料
型號(hào)： COLDFIRE2UMAD
英文描述： Version 2/2M ColdFire Core Processor User＇s Manual Addendum
中文描述： 版本2/2M ColdFire內(nèi)核的處理器用戶(hù)手冊(cè)附錄
文件頁(yè)數(shù)： 112/253頁(yè)
文件大?。?/td> 1762K
代理商： COLDFIRE2UMAD
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Integrated Memories
5-6
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
ACR are applied to the reference. If the address does not match either ACR, then the default
value defined in the Cache Control Register (CACR) is used. The specific algorithm is:
if (address = ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address = ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
5.1.6 Cache Coherency and Invalidation
The instruction cache does not monitor processor data references for accesses to cached
instructions. Therefore it is necessary for software to maintain cache coherence by
invalidating the appropriate cache entries after modifying code segments.
The cache invalidation can be performed in two ways:
1. The assertion of bit 24 in the Cache Control Register, via a CPU space write, forces the
entire instruction cache to be marked as invalid. The invalidation operation requires N (N =
# of lines) cycles since the cache sequences through the entire tag array clearing a single
location (the valid location) each cycle. Any subsequent instruction fetch accesses are
postponed until the invalidation sequence is complete; i.e. the processor can continue
running as long as it does not try and fetch from the instruction cache. If the instruction cache
is accessed, processing halts and waits for the invalidation to complete. The CACR can be
loaded to not turn on the instruction cache to let processing continue unblocked.
2. The privileged CPUSHL instruction can be used to invalidate a single cache line. When
this instruction is executed, the cache entry defined by bits [X:4] of the source address
register in invalidated, provided bit 28 of the CACR is cleared.
These invalidation operations may be initiated from the processor or the debug module.
5.1.7 Reset
A hardware reset clears the CACR disabling the instruction cache. The contents of the tag
array are not affected by the reset. Accordingly, the system start-up code must explicitly
perform a cache invalidation by setting CACR[24] before the cache may be enabled.
5.1.8 Line Fill Buffer and Cache Miss Fetch Algorithm
As discussed in Section 5.1.1, the instruction cache hardware includes a 16-byte line fill
buffer for providing temporary storage for the last fetched instruction.
With the cache enabled as defined by CACR[31], a cacheable instruction fetch that misses
in both the tag memory and the line-fill buffer generates an external fetch. The size of the
external fetch is determined by the value contained in the 2-bit CLNF field of the CACR, and
the miss address.
Table 5-3
shows the relationship between the CLNF bits, the miss
address and the size of the external fetch:
F
Freescale Semiconductor, Inc.
n
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
COLDFIRE3UM 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Version 3 ColdFire Core User＇s Manual
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