TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
MOTOROLA
ColdFire2/2M User’s Manual
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xiii
5.1.7
5.1.8
5.1.9
5.2
5.2.1
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
5.3.2
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.1.4
5.4.1.5
5.4.1.6
5.4.1.7
5.4.2
Cache Coherency...................................................................................5-6
Reset......................................................................................................5-6
Instruction Cache Programming Model ..................................................5-6
Access Control Registers ............................................................................5-8
ACR Programming Model.......................................................................5-8
ROM Module..............................................................................................5-10
ROM Signal Description .......................................................................5-10
ROM Address Bus (ROM_ADDR[14:2])..........................................5-11
ROM Data Output Bus (ROM_DO[31:0]).........................................5-11
ROM Enable (ROM_ENB[1:0])........................................................5-11
ROM Size (ROM_SZ[2:0])...............................................................5-12
ROM Valid (ROM_VLD)...................................................................5-12
ROM Programming Model....................................................................5-12
SRAM Module............................................................................................5-14
SRAM Signal Description .....................................................................5-14
SRAM Address Bus (SRAM_ADDR[14:2])......................................5-15
SRAM Chip-Select (SRAM_CSB)....................................................5-16
SRAM Data Input Bus (SRAM_DI[31:0]) .........................................5-16
SRAM Data Output Bus (SRAM_DO[31:0]).....................................5-16
SRAM Size (SRAM_SZ[2:0])...........................................................5-16
SRAM Strobe (SRAM_ST[3:0]) .......................................................5-16
SRAM Read/Write (SRAM_RWB[3:0]) ............................................5-16
SRAM Programming Model..................................................................5-16
Section 6
Multiply-Accumulate Unit
6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.4
6.5
Introduction..................................................................................................6-1
MAC Programming Model ...........................................................................6-2
Accumulator (ACC).................................................................................6-2
MAC Status Register (MACSR)..............................................................6-2
Mask Register (MASK)...........................................................................6-3
Shifting Operations......................................................................................6-4
Overflow Mode.............................................................................................6-4
MAC Instruction Set Summary ....................................................................6-5
Section 7
Debug Support
7.1
7.1.1
7.1.2
Signal Description........................................................................................7-1
Break Point (BKPTB)..............................................................................7-1
Debug Data (DDATA[3:0])......................................................................7-2
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