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參數(shù)資料
| 型號： | COLDFIRE2UMAD |
| 英文描述： | Version 2/2M ColdFire Core Processor User＇s Manual Addendum |
| 中文描述： | 版本2/2M ColdFire內(nèi)核的處理器用戶手冊附錄 |
| 文件頁數(shù)： | 105/253頁 |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE2UMAD |
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Exception Processing
4-12
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Interrupt requests should be maintained on the IPLB[2:0] signals until the conclusion of the
interrupt acknowledge (IACK) cycle from the processor to guarantee that the interrupt will
be recognized. The interrupt request can be maintained without being recognized again,
until the interrupt priority level in the SR is lowered below the currently requested level. This
is usually the result of the RTE instruction at the end of the interrupt exception handler.
Once the conclusion of an Interrupt Acknowledge (IACK) cycle occurs, another interrupt
may be asserted on the IPLB lines.The processor will start fetching the interrupt handler
code for the acknowledged interrupt. In the handler, the processor looks at the interrupt
mask level and determines if the second interrupt is masked or allowed.If the second
interrupt is not masked, the processor will start another IACK cycle for the second interrupt.
It will go to the second interrupt handler and sample IPLB inputs, compare mask, and
execute this handler if a higher level interrupt is not pending. Once the second interrupt has
completed the return from exception (RTE) in the handler, the processor will return to the
first interrupt handler, where the IPLB lines are sampled and compared to the interrupt
mask. If no interrupts have higher priority, it will execute this handler and return (RTE) to the
place in the code where the first interrupt was allowed to be taken.
Thus, interrupts can be nested, and higher interrupts given priority by the interrupt mask
register once they are executing code within the handlers.
4.2.11.1 LEVEL 7 INTERRUPTS.
levels one through six. A level 7 interrupt is a nonmaskable interrupt; therefore, a 7 in the
interrupt mask does not disable a level 7 interrupt.
Level 7 interrupts are handled differently than interrupt
Level 7 interrupts are edge-triggered by a transition from a lower priority request to the level
7 request, as opposed to interrupt levels one through six, which are level sensitive.
Therefore, if the interrupt priority level (IPLB[2:0]) signals remain at level 7, the ColdFire2/
2M will only recognize one level 7 interrupt since only one transition from a lower level
request to a level 7 request occurred. For the ColdFire2/2M to recognize a level 7 interrupt
followed by another level 7 interrupt, one of the two following sequences must occur:
1. The interrupt request level on the IPLB[2:0] signals changes from a lower request level
to level 7 and remains at level 7 until the interrupt acknowledge bus cycle begins.
Later, the interrupt request level returns to a lower interrupt request level and then
back to level 7, causing a second transition on the IPLB[2:0] signals.
2. The interrupt request level on the IPLB[2:0] signals changes from a lower request level
to level 7 and remains at level 7. If the interrupt handling routine for the level 7 interrupt
lowers the interrupt mask level, a second level 7 interrupt will be recognized even
though no transition has occurred on the interrupt control pins. After the level 7
interrupt handling routine completes, the ColdFire2/2M will compare the interrupt
mask level to the interrupt request level on the IPLB[2:0] signals. Since the interrupt
mask level will be lower than the requested level, the interrupt mask will be set back
to level 7. The level 7 request on the IPLB[2:0] signals must be held until the second
interrupt acknowledge bus cycle has begun to ensure that the interrupt is recognized.
4.2.11.2 SPURIOUS, AUTOVECTORED, AND UNINITIALIZED INTERRUPTS.
the external logic indicates an access error during the interrupt acknowledge cycle, the
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