
3
Intel
a
Celeron
Processor Mobile Module MMC-1
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
CONTENTS
1.0
INTRODUCTION...................................................5
Revision History................................................5
ARCHITECTURE OVERVIEW..............................5
MODULE CONNECTOR INTERFACE..................7
Signal Definition................................................7
3.1.1
Signal List.................................................8
3.1.2
Memory (108 Signals)...............................9
3.1.3.
PCI (56 Signals)......................................10
3.1.4
Processor and PIIX4E/M Sideband
(9 Signals).............................................11
3.1.5
Power Management (8 Signals)..............12
3.1.6
Clock (8 Signals).....................................13
3.1.7
Voltages (39 Signals)..............................14
3.1.8
JTAG (7 Signals)....................................14
3.1.9
Miscellaneous (45 Signals).....................15
3.2
Connector Pin Assignments............................16
3.3
Pin and Pad Assignments...............................18
FUNCTIONAL DESCRIPTION............................19
4.1
Celeron Processor Mobile Module MMC-1.....19
4.2
L2 Cache........................................................19
4.3
The 82443DX Host Bridge System Controller.19
4.3.1
Memory Organization.............................19
4.3.2
Reset Strap Options ...............................20
4.3.3
PCI Interface...........................................20
4.3.4
AGP Feature Set.....................................20
Power Management............................................20
4.4.1
Clock Control Architecture......................20
4.4.2
Normal State...........................................22
4.4.3
Auto Halt State........................................22
4.4.4
Stop Grant State.....................................22
4.4.5
Quick Start State.....................................22
4.4.6
HALT/Grant Snoop State........................22
4.4.7
Sleep State.............................................22
4.4.8
Deep Sleep State....................................23
1.1
2.0
3.0
3.1
4.0
4.4
4.5
4.6
Typical POS/STR Power.................................23
Electrical Requirements..................................24
4.6.1
DC Requirements ...................................24
4.6.2
AC Requirements....................................25
4.6.2.1
BCLK Signal Quality Specifications and
Measurement Guidelines ....................26
4.7
The Voltage Regulator....................................26
4.7.1
Voltage Regulator Efficiency...................26
4.7.2.
Control of the Voltage Regulator.............27
4.7.2.1
Voltage Signal Definition and
Sequencing.........................................28
4.7.3
Power Planes: Bulk Capacitance
Requirements..........................................29
4.7.4
Surge Current Guidelines .......................30
4.7.4.1
Slew-rate Control: Circuit Description.32
4.7.4.2
Undervoltage Lockout: Circuit
Description (V_uv_lockout).................33
4.7.4.3
Overvoltage Lockout: Circuit Description
(V_ov_lockout)....................................34
4.7.4.4
Overcurrent Protection: Circuit
Description..........................................34
4.8
Active Thermal Feedback...............................34
4.9
Thermal Sensor Configuration Register..........35
MECHANICAL SPECIFICATION........................35
5.1
Module Dimensions ........................................35
5.1.1
MMC-1 Connector Pin 1 Location...........36
5.1.2
Printed Circuit Board Thickness..............36
5.1.3
Height Restrictions .................................37
5.2
Thermal Transfer Plate....................................38
5.3
Physical Support.............................................39
5.3.1
Mounting Requirements..........................39
5.3.2
Module Weight........................................40
THERMAL SPECIFICATION...............................40
6.1
Thermal Design Power...................................40
6.2
Thermal Sensor Setpoint................................40
LABELING INFORMATION.................................41
ENVIRONMENTAL STANDARDS ......................42
5.0
6.0
7.0
8.0