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參數(shù)資料
| 型號： | Celeron Processor with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器1處理器) |
| 中文描述： | 賽揚處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫1（工作頻率四千〇三億六千六百三十三萬三千三百和266兆赫茲帶移動模塊和連接器1處理器） |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CELERON PROCESSOR WITH MOBILE |
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11
Intel
a
Celeron
Processor Mobile Module MMC-1
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
3.1.4
Processor and PIIX4E/M Sideband (9
Signals)
Table 4 lists the processor and PIIX4E/M sideband interface
signals. The voltage level for these signals is determined by
V_CPUIO.
Table 4. Processor/PIIX4E/M Sideband Signal Descriptions
Voltage
Description
Name
Type
FERR#
O
CMOS
V_CPUIO
Numeric Coprocessor Error:
This pin functions as a FERR# signal supporting
coprocessor errors. This signal is tied to the coprocessor error signal on the processor
and is driven by the processor to the PIIX4E/M
CPURST
N/C
CMOS
ID
CMOS
ID
CMOS
ID
CMOS
ID
CMOS
V_CPUIO
Processor Reset:
The signal is not used in the Celeron processor mobile module
MMC-1.
IGNNE#
V_CPUIO
Ignore Error:
This open-drain signal is connected to the Ignore Error pin on the
processor and is driven by the PIIX4E/M.
INIT#
V_CPUIO
Initialization:
INIT# is asserted by the PIIX4E/Mto the processor for system
initialization. This signal is an open-drain.
INTR
V_CPUIO
Processor Interrupt:
INTR is driven by the PIIX4E/Mto signal the processor that an
interrupt request is pending and needs to be serviced. This signal is an open-drain.
NMI
V_CPUIO
Non-Maskable Interrupt:
NMI is used to force a non-maskable interrupt to the
processor.
The PIIX4E/M ISA bridge generates NMI when either SERR# or IOCHK# is
asserted, depending on how the NMI Status and Control Register is programmed. This
signal is an open-drain.
A20M#
ID
CMOS
ID
CMOS
V_CPUIO
Address Bit 20 Mask:
When enabled, this open-drain signal causes the processor to
emulate the address wraparound at 1 MB, which occurs on the Intel 8086 processor.
SMI#
V_CPUIO
System Management Interrupt:
SMI# is an active low synchronous output from the
PIIX4E/M that is asserted in response to one of many enabled hardware or software
events.
The SMI# open-drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK#
ID
CMOS
V_CPUIO
Stop Clock:
STPCLK# is an active low synchronous open-drain output from the
PIIX4E/M that is asserted in response to one of many hardware or software events.
STPCLK# connects directly to the processor and is synchronous to PCICLK.
When the
processor samples STPCLK# asserted, it responds by entering a low power state (Quick
Start). The processor will only exit this mode when this signal is deasserted.
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| CELHK11-1REC5-71165-11-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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