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參數(shù)資料
| 型號： | Celeron Processor with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器1處理器) |
| 中文描述： | 賽揚處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫1（工作頻率四千〇三億六千六百三十三萬三千三百和266兆赫茲帶移動模塊和連接器1處理器） |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CELERON PROCESSOR WITH MOBILE |
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13
Intel
a
Celeron
Processor Mobile Module MMC-1
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
3.1.6
Clock (8 Signals)
Table 6 lists the clock interface signals.
Table 6. Clock Signal Descriptions
Name
Type
Voltage
Description
OEM_PD
I
CMOS
I
PCI
V_3
OEM Pulldown:
It is renamed from PCI_REF and is not required on the module.
PCLK
V_3S
PCI Clock In:
PCLK is an input to the module from the CKDM66-M clock source and is
one of the system’s PCI clocks.
This clock is used by all of the 82443DX Host Bridge
logic in the PCI clock domain.
This clock is stopped when the PIIX4E/M PCI_STP#
signal is asserted and/or during all suspend states.
HCLK[1:0]
I
CMOS
V_CPUIO
Host Clock In:
These clocks are inputs to the module from the CKDM66-M clock source
and are used by the processor and the 82443DX Host Bridge system controller. This
clock is stopped when the PIIX4E/M CPU_STP# signal is asserted and/or during all
suspend states.
SUSCLK
N/C
CMOS
O
CMOS
V_3
Suspend Clock
: This signal is not used on the module.
FQS[1:0]
V_3S
Frequency Status:
This signal provides the status of the host clock frequency to the
system electronics.
These signals are static and are pulled either low or high to the
V_3S voltage supply through a 10-K
resistor. This module is designed for the 66-MHz
strapping option shown below.
FQS1
0
0
1
1
FQS0
0
1
0
1
Frequency
60 MHz
66 MHz
Reserved
Reserved
CPU3.3_2.5#
O
CMOS
V_CPUIO
Clock Voltage Select:
Provides status to the system electronics about the voltage level
at which the CKDM66-M clock generator should be operating. This signal is pulled low
by module.
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