參數(shù)資料
型號(hào)： Celeron Processor with mobile
廠商： Intel Corp.
英文描述： Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器1處理器)
中文描述： 賽揚(yáng)處理器的移動(dòng)模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫1（工作頻率四千〇三億六千六百三十三萬三千三百和266兆赫茲帶移動(dòng)模塊和連接器1處理器）
文件頁(yè)數(shù)： 10/42頁(yè)
文件大?。?/td> 449K
代理商： CELERON PROCESSOR WITH MOBILE
10
Intel
a
Celeron
Processor Mobile Module MMC-1
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
3.1.3.
PCI (56 Signals)
Table 3 lists the PCI interface signals.
Table 3. PCI Signal Description
Name
Type
Voltage
Description
AD[31:0]
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
V_3
Address/Data:
The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in following clocks.
C/BE[3:0]#
V_3
Command/Byte Enable:
The command is driven with FRAME# assertion and byte
enables corresponding to supplied or requested data is driven on the following clocks.
FRAME#
V_3
Frame:
Assertion indicates the address phase of a PCI transfer. Negation indicates that
the cycle initiator desires one more data transfer.
DEVSEL#
V_3
Device Select:
The 82443DX Host Bridge drives this signal when a PCI initiator is
attempting to access DRAM.
DEVSEL# is asserted at medium decode time.
IRDY#
V_3
Initiator Ready:
Asserted when the initiator is ready for data transfer.
TRDY#
V_3
Target Ready:
Asserted when the target is ready for data transfer.
STOP#
V_3
Stop:
Asserted by the target to request the master to stop the current transaction.
PLOCK#
V_3
Lock:
Indicates an exclusive bus operation and may require multiple transactions to
complete. When LOCK# is asserted, nonexclusive transactions may proceed. The
82443DX supports lock for CPU initiated cycles only. PCI initiated locked cycles are not
supported.
REQ[4:0]#
I
PCI
O
PCI
I
PCI
V_3
PCI Request:
PCI master requests for PCI.
GNT[4:0]#
V_3
PCI Grant:
Permission is given to the master to use PCI.
PHOLD#
V_3
PCI Hold:
This signal comes from the expansion bridge; it is the bridge request for PCI.
The 82443DX Host Bridge will drain the DRAM write buffers, drain the processor-to-PCI
posting buffers, and acquire the host bus before granting the request via PHLDA#. This
ensures that GAT timing is met for ISA masters.
The PHOLD# protocol has been
modified to include support for passive release.
PHLDA#
O
PCI
V_3
PCI Hold Acknowledge:
The 82443DX Host Bridge drives this signal to grant PCI to
the expansion bridge. The PHLDA# protocol has been modified to include support for
passive release.
PAR
I/O
PCI
I/O
PCI
I/O D
PCI
V_3
Parity:
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
SERR#
V_3
System Error:
The 82443DX asserts this signal to indicate an error condition. Please
refer to the
Intel
a
440BX PCIset Datasheet
for further information.
CLKRUN#
V_3
Clock Run:
An open-drain output and input.
The 82443DX Host Bridge requests the
central resource (PIIX4E/M) to start or maintain the PCI clock by asserting CLKRUN#.
The 82443DX Host Bridge tri-states CLKRUN# upon deassertion of Reset (since CLK is
running upon deassertion of Reset).
PCI_RST#
I
CMOS
V_3
Reset:
When asserted, this signal asynchronously resets the 82443DX Host Bridge.
The PCI signals also tri-state, compliant with the
PCI Rev 2.1 specifications
.
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