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參數(shù)資料
| 型號： | Celeron Processor with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器1處理器) |
| 中文描述： | 賽揚處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫1（工作頻率四千〇三億六千六百三十三萬三千三百和266兆赫茲帶移動模塊和連接器1處理器） |
| 文件頁數(shù)： | 14/42頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CELERON PROCESSOR WITH MOBILE |
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14
Intel
a
Celeron
Processor Mobile Module MMC-1
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
3.1.7
Voltages (39 Signals)
Table 7 lists the voltage signal definitions.
Table 7. Voltage Descriptions
Name
Type
Number
of Pins
Description
V_DC
I
10
DC Input:
5V-21V.
V_3S
I
20
SUSB# controlled 3.3V:
V_3S is supplied by the system electronics. This is a 3.3-V power
supply that is turned off during suspend during system states STR, STD, and Soff.
V_5
I
1
SUSC# controlled 5V:
Power managed 5.0-V supply.
An output of the voltage regulator on
the system electronics. This rail is off during STD and Soff.
V_3
I
5
SUSC# controlled 3.3V:
Power managed 3.3-V supply.
An output of the voltage regulator on
the system electronics. This rail is off during STD and Soff.
V_CPUIO
O
3
Processor I/O Ring:
Powers the processor interface signals such as the PIIX4E/M open-drain
pullups for the processor/PIIX4E/Msideband signals and the CKDM66-M clock source.
3.1.8
JTAG (7 Signals)
Table 8 lists the JTAG signals, which the system electronics
can use to implement a JTAG chain and ITP port, if desired.
The JTAG signals provided can not be used as an ITP port.
Table 8. JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUIO
JTAG Test Data Out:
Serial output port. TAP instructions and data is shifted out of the
processor from this port.
TDI
I
V_CPUIO
JTAG Test Data In:
Serial input port. TAP instructions and data is shifted into the
processor from this port.
TMS
I
V_CPUIO
JTAG Test Mode Select:
Controls the TAP controller change sequence.
TCLK
I
V_CPUIO
JTAG Test Clock:
Testability clock for clocking the JTAG boundary scan sequence.
TRST#
I
V_CPUIO
JTAG Test Reset:
Asynchronously resets the TAP controller in the processor.
ITP(1:0)
ITP1
ITP0
O
I
V_CPUIO
Debug Port Signals:
These signals are not used in the Celeron processor mobile
module MMC-1and should not be connected.
NOTE:
DBREST# (reset target system) on the ITP debug port can be “l(fā)ogically ANDed” with VR_PWRGD TO PIIX4E/M’s PWROK.
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