參數(shù)資料
型號(hào)： CDB8420
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 82/94頁(yè)
文件大?。?/td> 0K
描述： EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻，采樣率轉(zhuǎn)換器
嵌入式： 是，MCU，8 位
已用 IC / 零件： CS8420
主要屬性： 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性： 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI
已供物品： 板
相關(guān)產(chǎn)品： 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱： 598-1782
DS245F4
83
CS8420
.
15.1.2
Reserving the First 5 Bytes in the E Buffer
D-to-E buffer transfers periodically overwrite the data stored in the E buffer. This can be a problem for
users who want to transmit certain channel status settings which are different from the incoming settings.
In this case, the user would have to superimpose his settings on the E buffer after every D-to-E overwrite.
To avoid this problem, the CS8420 has the capability of reserving the first 5 bytes of the E buffer for user
writes only. When this capability is in use, internal D-to-E buffer transfers will NOT affect the first 5 bytes
of the E buffer. Therefore, the user can set values in these first 5 E bytes once, and the settings will persist
until the next user change. This mode is enabled via the Channel Status Data Buffer Control register.
15.1.3
Serial Copy Management System (SCMS)
In Software mode, the CS8420 allows read/modify/write access to all the channel status bits. For Con-
sumer mode SCMS compliance, the host microcontroller needs to read and manipulate the Category
Code, Copy bit and L bit appropriately.
In Hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG input pins,
or by using the C bit serial input pin. These options are documented in the Hardware mode section of this
15.1.4
Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the
LS Byte is the B channel data (see Figure 37).
There are two methods of accessing this memory, known as one-byte mode and two-byte mode. The de-
sired mode is selected via a control register bit.
E to Finterrupt occurs
Optionally set E to F inhibit
Clear D to E inhibit
If set, clear E to F inhibit
Return
Set D to E inhibit
Write E data
Wait for E to F transfer
Figure 40. Flowchart for Writing the E Buffer
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