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參數(shù)資料
| 型號(hào)： | CDB8420 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 17/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS8420 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS8420 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC |
| 其它名稱： | 598-1782 |
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24
DS245F4
CS8420
7.1.6
Non-Audio Auto Detection
Since it is possible to convey non-audio data in an AES3 data stream, it is important to know whether the
incoming AES3 data stream is digital audio or other data. This information is typically conveyed in channel
status bit 1 (AUDIO), which is extracted automatically by the CS8420. However, certain non-audio sourc-
es, such as AC-3 or MPEG encoders, may not adhere to this convention, and the bit may not be properly
set. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a
96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync
code is detected, an internal AUTODETECT signal will be asserted. If no additional sync codes are de-
tected within the next 4096 frames, AUTODETECT will be de-asserted until another sync code is detect-
ed. The AUDIO bit in the Receiver Channel Status register is the logical OR of AUTODETECT and the
received channel status bit 1. If non-audio data is detected, the data is still processed exactly as if it were
normal audio. It is up to the user to mute the outputs as required.
7.2
AES3 Transmitter
The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and
bi-phase mark-encoded. The resulting bit stream is then driven directly, or through a transformer, to an
output connector.
The transmitter is usually clocked from the output side clock domain of the sample rate converter. This
clock may be derived from the clock input pin OMCK, or from the incoming data. In data flows with no
SRC, and where OMCK is asynchronous to the data source, an interrupt bit is provided that will go high
every time a data sample is dropped or repeated.
The channel status (C) and user channel (U) bits in the transmitted data stream are taken from storage
areas within the CS8420. The user can manipulate the contents of the internal storage with a microcon-
troller. The CS8420 will also run in one of several automatic modes. “Channel Status and User Data Buffer
Management” on page 81 provides detailed descriptions of each automatic mode, and describes methods
for accessing the storage areas. The transmitted user data can optionally be input via the U pin, under the
control of a control port register bit. Figure 20 shows the timing requirements for inputting U data via the
U pin.
7.2.1
Transmitted Frame and Channel Status Boundary Timing
The TCBL pin may be an input or an output, and is used to control or indicate the start of transmitted chan-
nel status block boundaries.
In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame
boundaries. This may be achieved in 3 ways:
1) With TCBL configured as an input, and TCBL transitions high for >3 OMCK clocks, it will cause a frame
start, and a new channel status block start.
2) If the AES3 output comes from the AES3 input, while there is no SRC, setting TCBL as output will cause
AES3 output frame boundaries to align with AES3 input frame boundaries.
3) If the AES3 output comes from the serial audio input port while the port is in Slave mode, and TCBL is
set to output, then the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.
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