參數(shù)資料
型號(hào)： CDB8420
廠(chǎng)商： Cirrus Logic Inc
文件頁(yè)數(shù)： 36/94頁(yè)
文件大小： 0K
描述： EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻，采樣率轉(zhuǎn)換器
嵌入式： 是，MCU，8 位
已用 IC / 零件： CS8420
主要屬性： 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性： 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI
已供物品： 板
相關(guān)產(chǎn)品： 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱(chēng)： 598-1782
DS245F4
41
CS8420
10.9
Interrupt Register 2 Status (08h) (Read Only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least
once since the register was last read. A”0” means the associated interrupt condition has NOT
occurred since the last reading of the register. Reading the register resets all bits to 0, unless
the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked
off in the associated mask register will always be “0” in this register. This register defaults to 00.
VFIFO
Varispeed FIFO overflow indicator. Occurs if the data buffer in the SRC overflows. This will oc-
cur if the input sample rate slows too fast.
REUNLOCK
Sample rate converter unlock indicator. This interrupt occurs if the SRC is still tracking a chang-
ing input or output sample rate.
DETU
D to E U-buffer transfer interrupt. The source of this bit is true during the D to E buffer transfer
in the U bit buffer management process (block mode only).
EFTU
E to F U-buffer transfer interrupt. The source of this bit is true during the E to F buffer transfer
in the U bit buffer management process (block mode only).
QCH
A new block of Q-subcode data is available for reading. The data must be completely read with-
in 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block.
UOVW
U-bit FIFO Overwrite. This interrupt occurs on an overwrite in the U-bit FIFO.
10.10 Interrupt 1 Register Mask (09h)
The bits of this register serve as a mask for the Interrupt 1 Register. If a mask bit is set to 1, the error is
considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask
bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the
status register. The bit positions align with the corresponding bits in Interrupt Register 1. This register de-
faults to 00.
10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. This code deter-
mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt
condition, or on the continuing occurrence of the interrupt condition. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
7
6
5
4
3
210
0
VFIFO
REUNLOCK
DETU
EFTU
QCH
UOVW
7
6
5
4
3
210
TSLIPM
OSLIPM
SREM
OVRGLM
OVRGRM
DETCM
EFTCM
RERRM
7
6
5
4
3210
TSLIP1
OSLIP1
SRE1
OVRGL1
OVRGR1
DETC1
EFTC1
RERR1
TSLIP0
OSLIP0
SRE0
OVRGL0
OVRGR0
DETC0
EFTC0
RERR0
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