參數(shù)資料
型號(hào): CDB8420
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 28/94頁(yè)
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻,采樣率轉(zhuǎn)換器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS8420
主要屬性: 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性: 44.1、48、96 kHz 輸出采樣率,AES/EBU,S/PDIF,EIAJ-340,GUI
已供物品:
相關(guān)產(chǎn)品: 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱: 598-1782
34
DS245F4
CS8420
10.2
Miscellaneous Control 1 (01h)
SWCLK
Causes OMCK to be output through the RMCK pin when the PLL is unlocked
0 - RMCK is driven by the PLL VCO (default)
1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driv-
en by the PLL is driven by OMCK.
VSET
Transmitted V bit level
0 - Transmit a 0 for the V bit, indicating that the data is valid, and is normally linear PCM audio
(default)
1 - Transmit a 1 for the V bit, indicating that the data is invalid or is not linear PCM audio data
MUTESAO
Mute control for the serial audio output port
0 - Normal output (default)
1 - Mute the serial audio output port
MUTEAES
Mute control for the AES3 transmitter output
0 - Normal output (default)
1 - Mute the AES3 transmitter output
DITH
Dither Control
0 - Triangular PDF dither applied to output data. The level of the dither is automatically adjusted
to be appropriate for the output word length selected by the SORES bits (default)
1 - No dither applied to output data.
INT[1:0]
Interrupt (INT) output pin control
00 - Active high, high output indicates an interrupt condition has occurred (default)
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin.
11 - Reserved
TCBLD
Transmit Channel Status Block pin (TCBL) direction specifier
0 - TCBL is an input (default)
1 - TCBL is an output
7
6
5
4
32
10
SWCLK
VSET
MUTESAO
MUTEAES
DITH
INT1
INT0
TCBLD
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