參數(shù)資料
型號(hào)： CDB8420
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 31/94頁(yè)
文件大小： 0K
描述： EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻，采樣率轉(zhuǎn)換器
嵌入式： 是，MCU，8 位
已用 IC / 零件： CS8420
主要屬性： 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性： 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI
已供物品： 板
相關(guān)產(chǎn)品： 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱(chēng)： 598-1782
DS245F4
37
CS8420
10.5
Clock Source Control (04h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow
Control register, various Receiver/Transmitter/Transceiver modes may be selected.
RUN
The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a
“powered down”, low current consumption, state.
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
control port is operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low (default).
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
CLK[1:0]
Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If
these bits are changed during normal operation, then always stop the CS8420 first (RUN = 0),
then write the new value, then start the CS8420 (RUN = 1).
00 - OMCK frequency is 256*Fso(default)
01 - OMCK frequency is 384*Fso
10 - OMCK frequency is 512*Fso
11 - reserved
OUTC
Output Time Base
0 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0,
(default)
1 - Recovered Input Clock
INC
Input Time Base Clock Source
0 - Recovered Input Clock (default)
1 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0)
RXD[1:0]
Recovered Input Clock Source
00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when the
serial audio input port is in Slave mode, default)
01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate
10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3
receiver is held in synchronous reset. This setting is useful to prevent UNLOCK
interrupts when using an external RMCK and inputting data via the serial audio
input port.
11 - Reserved
7
6
5
4
32
10
0
RUN
CLK1
CLK0
OUTC
INC
RXD1
RXD0
相關(guān)PDF資料
PDF描述
VI-J11-EX CONVERTER MOD DC/DC 12V 75W
GEM28DTAT CONN EDGECARD 56POS R/A .156 SLD
6278895-7 C/A 62.5/125 RIS SC MTRJ 7M1
A3BBB-2436G IDC CABLE- ASR24B/AE24G/ASR24B
GSM12DTAN CONN EDGECARD 24POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB8421 功能描述:音頻 IC 開(kāi)發(fā)工具 2-Ch 32-Bit 192kHz sample rate converte RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB8422 功能描述:界面開(kāi)發(fā)工具 Eval Bd 192kHz SRC S/PDIF Receiver RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
CDB8427 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd 96kHz Dig. Audio Transcvr RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB8952 制造商:Cirrus Logic 功能描述:NOT RECOMMENDED FOR NEW DESIGNS - USE CDB8952T - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con
CDB8952T 功能描述:以太網(wǎng)開(kāi)發(fā)工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*