參數(shù)資料
型號: CDB8420
廠商: Cirrus Logic Inc
文件頁數(shù): 47/94頁
文件大小: 0K
描述: EVALUATION BOARD FOR CS8420
標準包裝: 1
主要目的: 音頻,采樣率轉(zhuǎn)換器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS8420
主要屬性: 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性: 44.1、48、96 kHz 輸出采樣率,AES/EBU,S/PDIF,EIAJ-340,GUI
已供物品:
相關產(chǎn)品: 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱: 598-1782
DS245F4
51
CS8420
12. SOFTWARE MODE - PIN DESCRIPTION
The above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some pins
change their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a
*, and will be described once in this section. Pins marked with a + are used upon reset to select various start-up
options, and require a pull-up or pull-down resistor.
Power Supply Connections:
VD+ - Positive Digital Power *
Positive supply for the digital section. Nominally +5.0 V.
VA+ - Positive Analog Power *
Positive supply for the analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on
this pin will directly affect the jitter performance of the recovered clock.
DGND - Digital Ground *
Ground for the digital section. DGND should be connected to the same ground as AGND.
AGND - Analog Ground *
Ground for the analog section. AGND should be connected to the same ground as DGND.
Clock-Related Pins:
OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate (Fso).
RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample rate (Fsi).
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