參數(shù)資料
型號(hào)： CDB8420
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 55/94頁(yè)
文件大?。?/td> 0K
描述： EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻，采樣率轉(zhuǎn)換器
嵌入式： 是，MCU，8 位
已用 IC / 零件： CS8420
主要屬性： 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性： 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI
已供物品： 板
相關(guān)產(chǎn)品： 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱(chēng)： 598-1782
DS245F4
59
CS8420
13.3
Hardware Mode 2 Description
(DEFAULT Data Flow, Serial Input)
Hardware Mode 2 data flow is shown in Figure 25. Audio data is input via the serial audio input port, and
rate converted. The audio data at the new rate is then output both via the serial audio output port and via
the AES3 transmitter.
The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVEN pin.
When CUVEN is low, mode 2A is selected, where COPY/C, ORIG/U, and EMPH/V pins allow selected
channel status data bits to be set. The COPY and ORIG pins are used to set the pro bit, the copy bit, and
the L bit, as shown in Table 9. In consumer mode, the transmitted category code shall be 0101100b, which
indicates sample rate converter. The transmitted U and V bits are zero.When the CUVEN pin is high, mode
2B is selected, where COPY/C, ORIG/U, and EMPH/V become serial bit inputs for C, U, and V data. This
data is clocked by both edges of OLRCK, and the channel status block start is indicated or determined by
TCBL. Figure 20 shows the timing requirements.
Audio serial port data formats are selected as shown in Tables 6, 7 and 10.
Start-up options are shown in Table 11, and allow choice of the serial audio output port as a master or slave
and whether TCBL is an input or an output. The serial audio input port is always a slave.
AES3
Encoder
&Tx
Serial
Audio
Output
Serial
Audio
Input
Sample
Rate
Converter
C&Ubit Data Buffer
Clocked by
Output Clock
Clocked by
Input Derived Clock
ILRCK
ISCLK
OLRCK
OSCLK
SDOUT
TXP
TXN
RMCK
LOCK
COPY/C ORIG/U EMPH/V CUVEN TCBL
DFC0
DFC1
S/AES
VD+
H/S
Output
Clock
Source
OMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
areomittedfromthis diagram. Please refer to the Typical Connection Diagram for hook-up details.
VD+
SDIN
SFMT1 SFMT0
Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input
相關(guān)PDF資料
PDF描述
VI-J11-EX CONVERTER MOD DC/DC 12V 75W
GEM28DTAT CONN EDGECARD 56POS R/A .156 SLD
6278895-7 C/A 62.5/125 RIS SC MTRJ 7M1
A3BBB-2436G IDC CABLE- ASR24B/AE24G/ASR24B
GSM12DTAN CONN EDGECARD 24POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB8421 功能描述:音頻 IC 開(kāi)發(fā)工具 2-Ch 32-Bit 192kHz sample rate converte RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB8422 功能描述:界面開(kāi)發(fā)工具 Eval Bd 192kHz SRC S/PDIF Receiver RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
CDB8427 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd 96kHz Dig. Audio Transcvr RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB8952 制造商:Cirrus Logic 功能描述:NOT RECOMMENDED FOR NEW DESIGNS - USE CDB8952T - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con
CDB8952T 功能描述:以太網(wǎng)開(kāi)發(fā)工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*