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參數(shù)資料
| 型號： | CDB8420 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 80/94頁 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS8420 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS8420 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC |
| 其它名稱： | 598-1782 |
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DS245F4
81
CS8420
15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8420 has a comprehensive channel status (C) and user (U) data buffering scheme, which allows automatic
management of channel status blocks and user data. Alternatively, sufficient control and access is provided to allow
the user to completely manage the C and U data via the control port.
15.1
AES3 Channel Status(C) Bit Management
The CS8420 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port.
Unlike the audio data, it is not possible to 'sample-rate' convert the C bits. This is because specific meanings
are associated with fixed-length data patterns, which should not be altered. Since the output data rate of the
CS8420 will differ from the input rate when sample-rate conversion is done, it is not feasible to directly trans-
fer incoming C data to the output. The CS8420 manages the flow of channel status data at the block level,
meaning that entire blocks of channel status information are buffered at the input, synchronized to the output
timebase, and then transmitted. The buffering scheme involves a cascade of three block-sized buffers,
named D,E, and F as shown in Figure 37. The MSB of each byte represents the first bit in the serial C data
stream. For example, the MSB of byte 0 (which is at control port address 20h) is the consumer/professional
bit for channel status block A.
The first buffer, D, accepts incoming C data from the AES receiver. The 2nd buffer, E, accepts entire blocks
of data from the D buffer. The E buffer is also accessible from the control port, allowing read and writing of
the C data. The 3rd buffer (F) is used as the source of C data for the AES3 transmitter. The F buffer accepts
block transfers from the E buffer.
If the input rate is slower than the output rate (so that in a given time interval, more channel status blocks
are transmitted than received), some buffered C blocks will be transmitted multiple times. If the input rate is
faster than the output rate, some will not be transmitted at all. This is illustrated in (Figure 38). In this manner,
channel status block integrity is maintained. If the transmitted sample count bits are important in the appli-
cation, then they will need to be updated via the control port by the microcontroller for every outgoing block.
Control Port
From
AES3
Receiver
To
AES3
Transmitter
E
24
words
8-bits
AB
DF
Received
Data
Buffer
Transmit
Data
Buffer
Figure 37. Channel Status Data Buffer Structure
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| CDB8952T | 功能描述:以太網(wǎng)開發(fā)工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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