參數(shù)資料
型號(hào)： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號(hào)8 KB的閃存MCU系列的ISP
文件頁數(shù)： 95/146頁
文件大?。?/td> 1856K
代理商： C8051F2XX
C8051F2xx
Rev. 1.6
95
SFR Definition 12.2. RSTSRC: Reset Source
(Note: Do not use read-modify-write operations on this register.)
Bit7:
Bit6:
Bit5:
RESERVED.
Not Used. Read only 0b.
C0RSEF: Comparator 0 Reset Enable and Flag
Write
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source (active low)
Read
Note: The value read from C0RSEF is not defined if Comparator 0 has not been enabled as
a reset source.
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0
SWRSF: Software Reset Force and Flag
Write
0: No Effect
1: Forces an internal reset. RST pin is not affected.
Bit4:
Read
0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag (Read only)
0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.
MCDRSF: Missing Clock Detector Flag (Read only)
0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.
PORSF: Power-On Reset Force and Flag
Write
0: No effect
1: Forces a Power-On Reset. RST is driven low.
Bit3:
Bit2:
Bit1:
Read
0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.
PINRSF: HW Pin Reset Flag
0: Source of prior reset was not from RST pin.
1: Source of prior reset was from RST pin.
Bit0:
R
R/W
R/W
R
R
R/W
R
Reset Value
-
C0RSEF
Bit5
SWRSEF WDTRSF MCDRSF
Bit4
Bit3
PORSF
Bit1
PINRSF
Bit0
xxxxxxxx
Bit7
Bit6
Bit2
SFR Address:
0xEF
相關(guān)PDF資料
PDF描述
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