參數(shù)資料
型號： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù)： 40/146頁
文件大?。?/td> 1856K
代理商： C8051F2XX
C8051F2xx
40
Rev. 1.6
6.
ADC (12-Bit, C8051F206 Only)
Description
The ADC subsystem for the C8051F206 consists of configurable analog multiplexer (AMUX), a program-
mable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector (see Figure 6.1). The AMUX, PGA, Data Conversion
Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ter's shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the
ADCEN bit in the ADC Control register (ADC0CN, Figure 6.5) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0.
Figure 6.1. 12-Bit ADC Functional Block Diagram
6.1.
Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0–1), and then the pin in the selected port (bits PINSL0–2) to be the analog
input.
The PGA amplifies the AMUX output signal by an amount determined by the states of the AMPGN2–0 bits
in the ADC Configuration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed
for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain of 1 on reset.
12-Bit
SAR
ADC
R
+
-
VDD
12
32-to-1
AMUX
VDD
ADCEN
S
X
AIN0
AIN31
ADBUSY(w)
C
AMX0SL
P
P
P
P
ADC0CF
A
A
A
A
A
A
ADC0CN
A
A
A
A
A
A
A
A
A
A
P
VDD
VREF
GND
T2 OV
.
ADC0LTL
ADC0LTH
24
12
ADWINT
AIN0-31 are port 0-3
pins -- any external
port pin may be configured
as an analog input
GND
A
ADC0GTL
ADC0GTH
Dig
Comp
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