參數(shù)資料
型號： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù)： 25/146頁
文件大小： 1856K
代理商： C8051F2XX
C8051F2xx
Rev. 1.6
25
4.
Pinout and Package Definitions
Table 4.1. Pin Definitions
Name
‘F206,
F220,
226,
230,
236
48-Pin 32-Pin
11,31
‘F221,
231
Type
Description
V
DD
GND
8
Digital Voltage Supply.
5,6,8,
13,32
9
Ground. (
Note:
Pins 5,6, and 8 on the 48-pin package are not
connected (NC), but it is recommended that they be connected to
ground.)
Monitor Enable (on 48 pin package ONLY). Enables reset volt-
age monitor function when pulled high (logic “1”).
JTAG Test Clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a
rising edge of TCK.
D Out JTAG Test Data Output. Data is shifted out on TDO on the falling
edge of TCK. TDO output is a tri-state driver.
A In
Crystal Input. This pin is the return for the internal oscillator cir-
cuit for a crystal or ceramic resonator. For a precision internal
clock, connect a crystal or ceramic resonator from XTAL1 to
XTAL2. If overdriven by an external CMOS clock, this becomes
the system clock.
A Out
Crystal Output. This pin is the excitation driver for a crystal or
ceramic resonator.
D I/O
Chip Reset. Open-drain output of internal Voltage Supply moni-
tor. Is driven low when V
DD
is < 2.7V and MONEN=1, or when a
‘1’is written to PORSF. An external source can force a system
reset by driving this pin low.
A I/O
Voltage Reference. When configured as an input, this pin is the
voltage reference for the ADC. Otherwise, V
DD
will be the refer-
ence. NOTE: this pin is Not Connected (NC) on ‘F230/1/6.
A In
Comparator 0 Non-Inverting Input.
A In
Comparator 0 Inverting Input.
D Out
Comparator 0 Output
A In
Comparator 1 Non-Inverting Input.
A In
Comparator 1 Inverting Input.
D Out
Comparator 1 Output
D I/O
A In
description).
D I/O
A In
description).
D I/O
A In
description).
MONEN
12
D In
TCK
TMS
TDI
25
26
28
17
18
20
D In
D In
D In
TDO
27
19
XTAL1
9
6
XTAL2
10
7
RST
14
10
VREF
7
5
CP0+
CP0-
CP0
CP1+
CP1-
CP1
P0.0/TX
4
3
2
1
4
3
2
1
32
31
28
48
47
40
Port0 Bit0. (See the Port I/O Sub-System section for complete
P0.1/RX
39
27
Port0 Bit1. (See the Port I/O Sub-System section for complete
P0.2/INT0
38
26
Port0 Bit2. (See the Port I/O Sub-System section for complete
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