參數(shù)資料
型號： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù)： 36/146頁
文件大小： 1856K
代理商： C8051F2XX
C8051F2xx
36
Rev. 1.6
SFR Definition 5.3. ADC0CN: ADC Control (C8051F220/1/6 and C8051F206)
Bit7:
ADCEN: ADC Enable Bit
0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.
ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b
ADSTM1–0: ADC Start of Conversion Mode Bits
00: ADC conversion started upon a write of 1 to ADBUSY
01: RESERVED
10: RESERVED
11: ADC conversions initiated on overflows of Timer 2
ADWINT: ADC Window Compare Interrupt Flag
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
ADLJST: ADC Left Justify Data Bit (Used on C8051F206 only)
0: Data in ADC0H:ADC0L registers are right justified.
1: Data in ADC0H:ADC0L registers are left justified.
Bit6:
Bit5:
Bit4:
Bits3–2:
Bit1:
Bit0:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ADCEN
Bit7
ADCTM
Bit6
ADCINT
Bit5
ADBUSY ADSTM1 ADSTM0 ADWINT
Bit4
Bit3
ADLJST
Bit0
(bit addressable)
00000000
Bit2
Bit1
SFR Address:
0xE8
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