參數(shù)資料
型號： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù)： 142/146頁
文件大?。?/td> 1856K
代理商： C8051F2XX
C8051F2xx
142
Rev. 1.6
JTAG Register Definition 18.4. FLASHDAT: JTAG Flash Data
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9–2:
Bit1:
DATA7–0: Flash Data Byte.
FAIL: Flash Fail Bit.
0:
Previous Flash memory operation was successful.
1:
Previous Flash memory operation failed. Usually indicates the associated memory
location was locked.
BUSY: Flash Busy Bit.
0:
Flash interface logic is not busy.
1:
Flash interface logic is processing a request. Reads or writes while BUSY = 1 will
not initiate another operation
Bit0:
JTAG Register Definition 18.5. FLASHSCL: JTAG Flash Scale
This register controls the Flash read timing circuit and the prescaler required to generate the correct
timing for Flash operations.
Bit7:
FOSE: Flash One-Shot Enable Bit.
0: Flash read strobe is a full clock-cycle wide.
1: Flash read strobe is 50nsec.
Bit6:
FRAE: Flash Read Always Bit.
0: The Flash output enable and sense amplifier enable are on only when needed to read the
Flash memory.
1: The Flash output enable and sense amplifier enable are always on. This can be used to
limit the variations in digital supply current due to switching the sense amplifiers, thereby
reducing digitally induced noise.
Bits5–4:
UNUSED. Read = 00b, Write = don't care.
Bits3–0:
FLSCL3–0: Flash Prescaler Control Bits.
The FLSCL3–0 bits control the prescaler used to generate timing signals for Flash opera-
tions. Its value should be written before any Flash write or erase operations are initiated.
The value written should be the smallest integer for which:
FLSCL[3:0] > log2(fSYSCLK / 50kHz)
Where fSYSCLK is the system clock frequency. All Flash read/write/erase operations are
disallowed when FLSCL[3:0] = 1111b.
Reset Value
DATA7 DATA6
Bit9
DATA5
Bit7
DATA4 DATA3 DATA2 DATA1
Bit6
Bit5
DATA0
Bit2
FAIL
Bit1
BUSY
Bit0
0000000000
Bit8
Bit4
Bit3
Reset Value
FOSE
Bit7
FRAE
Bit6
-
-
FLSCL3
Bit3
FLSCL2
Bit2
FLSCL1
Bit1
FLSCL0
Bit0
00000000
Bit5
Bit4
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相關代理商/技術參數(shù)
參數(shù)描述
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