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參數(shù)資料
| 型號(hào)： | C8051F2XX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Mixed Signal 8 kB ISP Flash MCU Family |
| 中文描述： | 混合信號(hào)8 KB的閃存MCU系列的ISP |
| 文件頁數(shù)： | 101/146頁 |
| 文件大?。?/td> | 1856K |
| 代理商： | C8051F2XX |
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C8051F2xx
Rev. 1.6
101
14. Port Input/Output
Description
The C8051F221/231 have three I/O Ports: Port0, Port1, and Port2. The C8051F206, C8051F220/6 and
C8051F230/6 have four I/O Ports: Port0, Port1, Port2, and Port3. A wide array of digital resources can be
assigned to these ports by the simple configuration of the port's corresponding multiplexer (MUX). Please
see Figure 8.1. Additionally, all external port pins are available as analog input.
14.1. Port I/O Initialization
Port I/O initialization is straightforward. Registers PRT0MX, PRT1MX and PRT2MX must be loaded with
the appropriate values to select the digital I/O functions required by the design. The output driver charac-
teristics of the I/O pins are defined using the Port Configuration Registers PRT0CF, PRT1CF, PRT2CF and
PRT3CF. Each Port Output driver can be configured as either Open Drain or Push-Pull. This is required
even for the digital resources selected in the PRTnMX registers, and is not automatic.
Any or all pins may be configured as digital I/O or as analog input. The default mode is digital I/O. The
P0MODE, P1MODE, P2MODE, and P3MODE special function registers are used to configure the port
pins as digital or analog as defined in this section.
The final step is initializing the individual resources selected using the appropriate setup registers. Initial-
ization procedures for the various digital resources may be found in the detailed explanation of each avail-
able function. The reset state of each register is shown in the figures that describe each individual register.
NOTE: The input mode of pins configured for use with Timer 0, 1, or 2 must be manually con-
figured.
1.
The output mode of all ports pins must be configured regardless of whether the port pin is
either standard general-purpose I/O or controlled by a digital peripheral.
For all pins used as Timer inputs (P0.4/T0, P0.5/T1, P0.6/T2, and P0.7/T2EX), the output
mode must be "open-drain" (which is the reset state), and "1" must be written to the associated
port pin to prevent possible contention for the port pin that could result in an overcurrent condi-
tion. For example, to configure a Timer0, set PRT0MX's T0E Timer0 enable bit to '1' to route
Timer0 to Port Pin P0.4. Then place P0.4/T0 in open-drain configuration (which is set in
PRT0CF by default), and write a '1' to P0.4 to set its output state to high impedance for use as
a digital peripheral input (port pins also default to logic high state upon reset). Lastly, ensure
P0MODE.4 is '1' for digital input mode. (All pins default to digital input mode upon reset.)
2.
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參數(shù)描述 |
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| C8051F300DK-A | 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035 |
| C8051F300DK-B | 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035 |
| C8051F300DK-E | 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035 |
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