參數(shù)資料
型號： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù)： 117/146頁
文件大?。?/td> 1856K
代理商： C8051F2XX
C8051F2xx
Rev. 1.6
117
16. UART
Description
The CIP-51 includes a serial port (UART) capable of asynchronous transmission. The UART can function
in full duplex mode. In all modes, receive data is buffered in a holding register. This allows the UART to
start reception of a second incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the
SFRs. The single SBUF location provides access to both transmit and receive registers. Reads access
the Receive register and writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a
Transmit Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Inter-
rupt flag, RI (SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manu-
ally by software. This allows software to determine the cause of the UART interrupt (transmit complete or
receive complete).
Figure 16.1. UART Block Diagram
SBUF
Shift
Load SBUF
SFR Bus
Input Shift Register
(9 bits)
Bit Detector
Read
SBUF
Rx Control
Start
Rx Clock
Load
SBUF
0x1FF
Shift
Tx Control
Tx Clock
Serial
Port
Interrupt
Tx IRQ
Zero Detector
Send
Shift
SBUF
SFR Bus
SET
Q
D
CLR
Stop Bit
Gen.
TB8
Start
01
10
11
00
SMOD
1
0
01
10
11
00
Timer 2
Overflow
TCLK
1
0
RCLK
1
0
Timer 1
Overflow
SCON
S
M
2
N
T
B
8
R
B
8
T
I
R
I
PCON
S
M
O
D
SMOD
Data
Write to
SBUF
S
M
1
S
M
0
R
E
Enable
REN
T2CON
R
C
L
K
K
T
C
L
SYSCLK
MSB
RB8
Rx IRQ
TI
RI
Port0 MUX
Baud Rate Generation Logic
Port0 MUX
RX
TX
Port I/O
1
0
32
64
12
SM0, SM1
{MODE}
16
16
2
P0.0
P0.1
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