參數(shù)資料
型號： C8051F2XX
廠商： Electronic Theatre Controls, Inc.
英文描述： Mixed Signal 8 kB ISP Flash MCU Family
中文描述： 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù)： 17/146頁
文件大?。?/td> 1856K
代理商： C8051F2XX
C8051F2xx
Rev. 1.6
17
Figure 1.6. Comparison of Peak MCU Throughputs
1.2.
On-Board Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. An optional 1024 bytes of XRAM is available on the 'F206,
'F226 and 'F236. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128-byte SFR address space. The lower 128 bytes of RAM are accessible via
direct or indirect addressing. The first 32 bytes are addressable as four banks of general purpose regis-
ters, and the next 16 bytes can be byte addressable or bit addressable.
The MCU's program memory consists of 8 k + 128 bytes of Flash. This memory may be reprogrammed in-
system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from
addresses 0x1E00 to 0x1FFF are reserved for factory use. There is also a user programmable 128-byte
sector at address 0x2000 to 0x207F, which may be useful as a table for storing software constants, nonvol-
atile configuration information, or as additional program space. See Figure 1.7 for the MCU system mem-
ory map.
WDT
CIP-51
Core
Missing
Clock
Detector
W
S
(Software Reset)
/RST
+
-
VDD
Supply
Reset
Timeout
(wired-OR)
System Reset
Supply
Monitor
PRE
Reset
Funnel
+
-
CP0+
Comparator 0
CP0-
C0RSEF
EN
W
E
EN
M
E
SWRSF
System
Clock
MonEn
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