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參數(shù)資料
| 型號： | C8051F2XX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Mixed Signal 8 kB ISP Flash MCU Family |
| 中文描述： | 混合信號8 KB的閃存MCU系列的ISP |
| 文件頁數(shù)： | 76/146頁 |
| 文件大?。?/td> | 1856K |
| 代理商： | C8051F2XX |
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C8051F2xx
76
Rev. 1.6
9.4.4. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP–EIP2) used to configure its
priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate.
9.4.5. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. NOTE: If a
Flash write or erase is performed, the MCU is stalled during the operation and interrupts will not be ser-
viced until the operation is complete. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and fol-
lowing instruction.
ADC0 End of Conversion
Software Controlled Interrupt 0
Software Controlled Interrupt 1
Software Controlled Interrupt 2
Software Controlled Interrupt 3
Unused Interrupt Location
External Crystal OSC Ready
0x007B
0x0083
0x008B
0x0093
0x009B
0x00A3
0x00AB
15
16
17
18
19
20
21
ADCINT (ADC0CN.5)
SCI0 (SWCINT.4)
SCI1 (SWCINT.5)
SCI2 (SWCINT.6)
SCI3 (SWCINT.7)
None
XTLVLD (OSCXCN.7)
EADC0 (EIE2.1)
ESCI0 (EIE2.2)
ESCI1 (EIE2.3)
ESCI2 (EIE2.4)
ESCI3 (EIE2.5)
Reserved (EIE2.6)
EXVLD (EIE2.7)
Table 9.4. Interrupt Summary (Continued)
Interrupt Source
Interrupt
Vector
Priority
Order
Interrupt-Pending Flag
Enable
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