參數(shù)資料
型號: C8051F2XX
廠商: Electronic Theatre Controls, Inc.
英文描述: Mixed Signal 8 kB ISP Flash MCU Family
中文描述: 混合信號8 KB的閃存MCU系列的ISP
文件頁數(shù): 20/146頁
文件大?。?/td> 1856K
代理商: C8051F2XX
C8051F2xx
20
Rev. 1.6
Figure 1.9. Port I/O Functional Block Diagram
1.5.
Serial Ports
The C8051F206, C8051F220/1/6 and C8051F230/1/6 include a Full-Duplex UART and SPI Bus. Each of
the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus
requiring very little intervention by the CPU. The serial buses do not have to "share" resources such as
timers, interrupts, or Port I/O, so both of the serial buses may be used simultaneously. (You may use
Timer1, Timer 2, or SYSCLK to generate baud rates for UART).
1.6.
Analog to Digital Converter
The C8051F220/1/6 has an on-chip 8-bit SAR ADC and the C8051F206 has a 12-bit SAR ADC with a pro-
grammable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 8-bit with an INL of
±1/4 LSB, and or 12-bit accuracy with ±2 LSB. The voltage reference can be the power supply (
V
DD
), or
an external reference voltage (VREF). Also, the system controller can place the ADC into a power-saving
shutdown mode when not in use. A programmable gain amplifier follows the analog multiplexer. The gain
can be set in software from 0.5 to 16 in powers of 2.
Conversions can be initiated in two ways; a software command or an overflow on Timer 2. This flexibility
allows the start of conversion to be triggered by software events, or convert continuously. A completed
conversion causes an interrupt, or a status bit can be polled in software to determine the end of conver-
sion. The resulting 8-bit data word is latched into an SFR upon completion of a conversion.
Port
1
MUX
PRTnMX
Registers
Port0 I/O Cell
Port1 I/O Cell
PRTnCF &
PnMODE
registers
T0,T1,T2
Timers
UART
External
INT0 & INT1
Comparators
0 & 1
P0.0/TX
P0.1/RX
P0.2/INT0
P0.3/INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
External
pins
Any port pin may be
configured via software as an
analog input to the ADC
Port
0
MUX
SYSCLK
Port
2
MUX
Port2 I/O Cell
Port3 I/O Cell
SPI
A
M
U
X
ADC
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
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