參數(shù)資料
型號: ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 92/141頁
文件大小: 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標準包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
54
ATmega103(L)
0945I–AVR–02/07
the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the
event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example.
Figure 35. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation, a read from OCR1A or
OCR1B will read the contents of the temporary location. This means that the most
recently written value always will read out of OCR1A/B.
When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated
t o low or h i gh o n th e ne xt co mpa r e ma tch a c cor d ing t o t he set t i ngs of
COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 20.
Note:
If the Compare Register contains the TOP value and the prescaler is not in use
(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-
counting and down-counting value is reached simultaneously. When the prescaler is in
use (CS12..CS10
≠ 001 or 000), the PWM output goes active when the counter reaches
the TOP value, but the down-counting compare match is not interpreted to be reached
before the next time the counter reaches the TOP value, making a one-period PWM
pulse.
Note:
X = A or B
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from
$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,
i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and Global
Interrupts are enabled. This does also apply to the Timer Output Compare1 flags and
interrupts.
Table 20. PWM Outputs OCR1X = $0000 or TOP
COM1X1
COM1X0
OCR1X
Output OC1X
1
0
$0000
L
10
TOP
H
1
$0000
H
11
TOP
L
Counter Value
Compare Value
PWM Output OC1X
Synchronized
OCR1X Latch
Counter Value
Compare Value
PWM Output OC1X
Unsynchronized
OCR1X Latch
Glitch
Compare Value changes
Note: X = A or B
Compare Value changes
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