參數(shù)資料
型號(hào)： ATMEGA103-6AI
廠商： Atmel
文件頁數(shù)： 125/141頁
文件大?。?/td> 0K
描述： IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 90
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 6MHz
連通性： SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
配用： ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
84
ATmega103(L)
0945I–AVR–02/07
Interface to External
SRAM
The interface to the SRAM consists of:
Port A: multiplexed low-order address bus and data bus
Port C: high-order address bus
The ALE pin: address latch enable
The RD and WR pin: read and write strobes
The external data SRAM is enabled by setting the external SRAM enable bit (SRE) of
the MCU Control Register (MCUCR) and will override the setting of the Data Direction
Register (DDRA). When the SRE bit is cleared (zero), the external data SRAM is dis-
abled and the normal pin and data direction settings are used. When SRE is cleared
(zero), the address space above the internal SRAM boundary is not mapped into the
internal SRAM as AVR parts do not have an interface to the external SRAM.
When ALE goes from high to low, there is a valid address on Port A. ALE is low during a
data transfer. RD and WR are active when accessing the external SRAM only.
When the external SRAM is enabled, the ALE signal may have short pulses when
accessing the internal RAM, but the ALE signal is stable when accessing the external
SRAM.
Figure 50 shows how to connect an external SRAM to the AVR using eight latches that
are transparent when G is high.
By default, the external SRAM access is a three-cycle scheme as depicted in Figure 51.
When one extra wait state is needed in the access cycle, set the SRW bit (one) in the
MCUCR Register. The resulting access scheme is shown in Figure 52. In both cases,
note that Port A is data bus in one cycle only. As soon as the data access finishes, Port
A becomes a low-order address bus again.
Note:
If a read is followed by a write, or vice versa, there is no extra insertion of wait states in
between. The user may insert a NOP between consecutive read and write operations to
the external RAM, because such short time for releasing the bus is difficult to obtain with-
out making bus contention.
For details on the timing for the SRAM interface, please refer to Figure 79, Table 45,
refer to “Architectural Overview” on page 8 for a description of the memory map, includ-
ing address space for SRAM.
Figure 50. External SRAM Connected to the AVR
D[7:0]
A[7:0]
A[15:8]
SRAM
WR
RD
DQ
G
Port A
ALE
Port C
AVR
RD
WR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATMEGA103L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash
ATMEGA103L-4AC 功能描述:8位微控制器 -MCU TQFP-64 128K FLASH 3 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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ATMEGA128 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash
ATMEGA128(L) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATmega128(L) Preliminary Summary [Updated 9/03. 23 Pages]
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