參數(shù)資料
型號(hào): ATMEGA103-6AI
廠商: Atmel
文件頁(yè)數(shù): 80/141頁(yè)
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤(pán)
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
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43
ATmega103(L)
0945I–AVR–02/07
These 8-bit registers contain the value of the Timer/Counters.
Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read
and write access. If the Timer/Counter is written to and a clock source is selected, it con-
tinues counting in the timer clock cycle after it is preset with the written value.
Timer/Counter0 Output
Compare Register – OCR0
Timer/Counter2 Output
Compare Register – OCR2
The Output Compare Registers are 8-bit read/write registers.
The Timer/Counter Output Compare Registers contain the data to be continuously com-
pared with the Timer/Counter. Actions on compare matches are specified in TCCR0 and
TCCR2. A compare match does only occur if the Timer/Counter counts to the OCR
value. A software write that sets the Timer/Counter and Output Compare Register to the
same value does not generate a compare match.
A compare match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
Timer/Counters 0 and 2 in
PWM Mode
When the PWM mode is selected, the Timer/Counter and the Output Compare Register
(OCR0 or OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with
outputs on the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin. The Timer/Counter acts as
an up/down counter, counting up from $00 to $FF, where it turns and counts down again
to zero before the cycle is repeated. When the counter value matches the contents of
the Output Compare Register, the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin is set or
cleared according to the settings of the COM01/COM00 or COM21/COM20 bits in the
Timer/Counter Control Registers TCCR0 and TCCR2. Refer to Table 13 for details.
Note:
n = 0 or 2
Note that in PWM mode, the Output Compare Register is transferred to a temporary
location when written. The value is latched when the Timer/Counter reaches $FF. This
prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn-
chronized OCR0 or OCR2 write. See Figure 32 for an example.
Bit
7
6
543
210
$31 ($51)
MSB
LSB
OCR0
Read/Write
R/WR/W
Initial Value
0
Bit
7
6
543
210
$23 ($43)
MSB
LSB
OCR2
Read/Write
R/WR/W
Initial Value
0
Table 13. Compare Mode Select in PWM Mode
COMn1
COMn0
Effect on Compare/PWM Pin
0
Not connected
0
1
Not connected
10
Cleared on compare match, up-counting. Set on compare match, down-
counting (non-inverted PWM).
11
Cleared on compare match, down-counting. Set on compare match, up-
counting (inverted PWM).
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