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| 型號(hào)： | ATMEGA103-6AI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 100/141頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 128K 6MHZ A/D IT 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | megaAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 6MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 128KB（64K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
| 配用： | ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU |
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61
ATmega103(L)
0945I–AVR–02/07
Figure 38. SPI Master-Slave Interconnection
The system is single-buffered in the transmit direction and double-buffered in the
receive direction. This means that characters to be transmitted cannot be written to the
SPI Data Register before the entire shift cycle is completed. When receiving data, how-
ever, a received byte must be read from the SPI Data Register before the next byte has
been completely shifted in. Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is
overridden according to the following table:
Note:
See “Alternate Functions of Port B” on page 89 for a detailed description and how to
define the direction of the user-defined SPI pins.
SS Pin Functionality
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine
the direction of the SS pin. If SS is configured as an output, the pin is a general output
pin that does not affect the SPI system. If SS is configured as an input, it must be held
high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry
when the SPI is configured as Master with the SS pin defined as an input, the SPI sys-
tem interprets this as another Master selecting the SPI as a Slave and starts to send
data to it. To avoid bus contention, the SPI system takes the following actions:
1.
The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a
result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2.
The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in
SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmittal is used in Master mode and there exists a
possibility that SS is driven low, the interrupt should always check that the MSTR bit is
still set. Once the MSTR bit has been cleared by a Slave Select, it must be set by the
user to re-enable SPI Master mode.
When the SPI is configured as a Slave, the SS pin is always input. When SS is held low,
the SPI is activated and MISO becomes an output if configured so by the user. All other
pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once
Table 22. SPI Pin Overrides
PIN
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
MASTER
MISO
SPI
CLOCK GENERATOR
SLAVE
MISO
MOSI MOSI
SCK
SS
V
CC
MSBLSB
MSB
LSB
8-BIT SHIFT REGISTER
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