參數(shù)資料
型號(hào): ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 119/141頁
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
79
ATmega103(L)
0945I–AVR–02/07
keeps running for as long as the ADEN bit is set and is continuously reset when ADEN
is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following falling edge of the ADC clock cycle. The actual sample-and-hold takes
place one ADC clock cycle after the start of the conversion. The result is ready and writ-
ten to the ADC Result Register after 13 cycles. The ADC needs two more clock cycles
before a new conversion can be started. If ADSC is set high in this period, the ADC will
start the new conversion immediately. For a summary of conversion times, see Table
Figure 47. ADC Timing Diagram, First Conversion
Figure 48. ADC Timing Diagram
Table 26. ADC Conversion Time
Condition
Sample
Cycle
Number
Result Ready
(Cycle
Number)
Total
Conversion
Time (Cycles)
Total
Conversion
Time (s)
1st Conversion
14
26
28
140 - 560
Single Conversion
1
13
15
75 - 300
MSB of result
LSB of result
ADC clock
ADSC
Hold strobe
ADIF
ADCH
ADCL
Cycle number
ADEN
1
212
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
Dummy Conversion
Actual Conversion
Second
Conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
MSB of result
LSB of result
ADC clock
ADSC
Hold strobe
ADIF
ADCH
ADCL
Cycle number
14
15
12
One Conversion
Next Conversion
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