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| 型號(hào)： | ATMEGA103-6AI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 72/141頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 128K 6MHZ A/D IT 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | megaAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 6MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 128KB（64K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
| 配用： | ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU |
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36
ATmega103(L)
0945I–AVR–02/07
(T im er/Co u n t er1 Ove r flow Inte rrup t En able) an d TO V1 a r e set (o ne) , th e
Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 advances from $0000.
Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and
the data in OCR0 – Output Compare Register 0. OCF0 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG and OCIE0 (Timer/Counter2
Compare Interrupt Enable) and the OCF0 are set (one), the Timer/Counter0 Output
Compare interrupt is executed.
Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(T im er/Co u n t er0 Ove r flow Inte rrup t En able) an d TO V0 a r e set (o ne) , th e
Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter0 advances from $00.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector
address for the actual interrupt handling routine is executed. During this four-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer
is decremented by 2. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is
popped back from the Stack, and the Stack Pointer is incremented by 2. When the AVR
exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Sleep Modes
To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register
select which sleep mode (Idle, Power-down, or Power-save) will be activated by the
SLEEP instruction, see Table 3 on page 23.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, exe-
cutes the interrupt routine and resumes execution from the instruction following SLEEP.
The contents of the Register File, SRAM, and I/O memory are unaltered. If a reset
occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Idle Mode
When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the
Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC,
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables
the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog
Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This
will reduce power consumption in Idle mode. When the MCU wakes up from Idle mode,
the CPU starts program execution immediately.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ATMEGA103L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| ATMEGA103L-4AC | 功能描述:8位微控制器 -MCU TQFP-64 128K FLASH 3 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATMEGA103L-4AI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash |
| ATMEGA128 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| ATMEGA128(L) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATmega128(L) Preliminary Summary [Updated 9/03. 23 Pages] |
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