參數(shù)資料
型號(hào)： ATMEGA103-6AI
廠商： Atmel
文件頁數(shù)： 121/141頁
文件大?。?/td> 0K
描述： IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 90
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 6MHz
連通性： SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
配用： ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
80
ATmega103(L)
0945I–AVR–02/07
ADC Noise Canceler
Function
The ADC features a noise canceler that enables conversion during Idle mode to reduce
noise induced from the CPU core. To make use of this feature, the following procedure
should be used:
1.
Turn off the ADC by clearing ADEN.
2.
Turn on the ADC and simultaneously start a conversion by setting ADEN and
ADSC. This starts a dummy conversion that will be followed by a valid
conversion.
3.
Within 14 ADC clock cycles, enter Idle mode.
4.
If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the MCU and execute the ADC conversion complete interrupt
routine.
ADC Multiplexer Select
Register – ADMUX
Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0
The value of these three bits selects which analog input 7 - 0 is connected to the ADC.
ADC Control and Status
Register – ADCSR
Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress will terminate this
conversion.
Bit 6 – ADSC: ADC Start Conversion
A logical “1” must be written to this bit to start each conversion. The first time ADSC has
been written after the ADC has been enabled, or if ADSC is written at the same time as
the ADC is enabled, a dummy conversion will precede the initiated conversion. This
dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the conversion is com-
plete, but before the result is written to the ADC Data Registers. This allows a new
conversion to be initiated before the current conversion is complete. The new conver-
sion will then start immediately after the current conversion completes. When a dummy
conversion precedes a real conversion, ADSC will stay high until the real conversion
completes.
Writing a zero to this bit has no effect.
Bit
7
6
543
210
$07 ($27)
–
MUX2
MUX1
MUX0
ADMUX
Read/Write
R
R/W
Initial Value
0
Bit
7654
321
0
$06 ($26)
ADEN
ADSC
–
ADIF
ADIE
ADPS2
ADPS1
ADPS0
ADCSR
Read/Write
R/W
R
R/W
Initial Value
0000
000
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ATMEGA103L-4AC 功能描述:8位微控制器 -MCU TQFP-64 128K FLASH 3 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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