- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1905 > ATMEGA103-6AI (Atmel)IC MCU 128K 6MHZ A/D IT 64TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ATMEGA103-6AI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 66/141頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 128K 6MHZ A/D IT 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | megaAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 6MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 128KB（64K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤(pán) |
| 配用： | ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)當(dāng)前第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)
30
ATmega103(L)
0945I–AVR–02/07
an external or Watchdog reset occurs, the source of reset can be found by using the fol-
lowing truth table, Table 8.
Interrupt Handling
The ATmega103(L) has two dedicated 8-bit Interrupt Mask Control Registers; EIMSK
(External Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).
In addition, other enable and mask bits can be found in the peripheral control registers.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the
flag is cleared by software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared
(zero), the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine or restored when returning from an interrupt routine. This must be handled by
software.
External Interrupt Mask
Register – EIMSK
Bits 7..4 – INT7 - INT4: External Interrupt Request 7 - 4 Enable
When an INT7 - INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Register (EICR) define whether the external inter-
rupt is activated on rising or falling edge or is level-sensed. Activity on any of these pins
will trigger an interrupt request even if the pin is enabled as an output. This provides a
way of generating a software interrupt.
Table 8. Reset Source Identification
Reset Source
EXTRF
PORF
Watchdog Reset
0
Power-on Reset
0
1
External Reset
1
0
Power-on Reset
1
Bit
7
6
5
4
3
2
1
0
$39 ($59)
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
EIMSK
Read/Write
R/W
Initial Value
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATMEGA128A-AUR | MCU AVR 128K FLASH 16MHZ 64TQFP |
| ATMEGA128L-8MJ | IC MCU AVR 128K 8MHZ LV 64-QFN |
| ATMEGA16-16MUR | MCU AVR 16KB FLASH 16MHZ 44QFN |
| ATMEGA164PA-AN | IC MCU AVR 16K FLASH 44TQFP |
| ATMEGA164PA-CUR | MCU AVR 16KB FLASH 20MHZ 49VFBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATMEGA103L | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| ATMEGA103L-4AC | 功能描述:8位微控制器 -MCU TQFP-64 128K FLASH 3 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATMEGA103L-4AI | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash |
| ATMEGA128 | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| ATMEGA128(L) | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ATmega128(L) Preliminary Summary [Updated 9/03. 23 Pages] |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。