參數(shù)資料
型號(hào): AM79C978AKCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Single-Chip 1/10 Mbps PCI Home Networking Controller
中文描述: 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 86/256頁
文件大?。?/td> 3505K
代理商: AM79C978AKCW
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86
Am79C978A
The LED pins can be configured to operate in either open-
drain mode (active low) or in totem-pole mode (active
high). The output can be stretched to allow the human
eye to recognize even short events that last only several
microseconds. After H_RESET, the five LED outputs are
configured as shown in Table 20.
Table 20.
LED Default Configuration
For each LED register, each of the status signals is AND
d
with its enable signal, and these signals are all OR
d to-
gether to form a combined status signal. Each LED pin
combined status signal can be programmed to run to a
pulse stretcher, which consists of a 3-bit shift register
clocked at 38 Hz (26 ms). The data input of each shift reg-
ister is normally at logic 0. The OR gate output for each
LED register asynchronously sets all three bits of its shift
register when the output becomes asserted. The inverted
output of each shift register is used to control an LED pin.
Thus, the pulse stretcher provides two to three clocks of
stretched LED output, or 52 ms to 78 ms. See Figure 46.
Power Savings Mode
Power Management Support
The controller supports power management as defined in
the PCI Bus Power Management Interface Specification
V1.1 and Network Device Class Power Management Ref-
erence Specification V1.0a.These specifications define
the network device power states, PCI power manage-
ment interface including the Capabilities Data Structure
and power management registers block definitions,
power management events, and OnNow network wake-
up events.
The general scheme for the Am79C978A power manage-
ment is that when a PCI wake-up event is detected, a sig-
nal is generated to cause hardware external to the
Am79C978A device to put the computer into the working
(S0) mode.
Figure 46.
LED Control Logic
The Am79C978A device supports three types of wake-up
events:
1. Magic Packet Detect
2. OnNow Pattern Match Detect
3. Link State Change
Figure 47 shows the relationship between these wake-
up events and the various outputs used to signal to the
external hardware.
OnNow Wake-Up Sequence
The system software enables the PME pin by setting the
PME_EN bit in the PMCSR register (PCI configuration
registers, offset 44h, bit 8) to 1. When a wake-up event is
detected, the controller sets the PME_STATUS bit in the
PMCSR register (PCI configuration registers, offset 44h,
bit 15). Setting this bit causes the PME signal to be as-
serted. Assertion of the PME signal causes external hard-
ware to wake up the CPU. The system software then
reads the PMCSR register of every PCI device in the sys-
tem to determine which device asserted the PME signal.
When the software determines that the signal came
from the controller, it writes to the device's PMCSR to
put the device into power state D0. The software then
writes a 0 to the PME_STATUS bit to clear the bit and
turn off the PME signal, and it calls the device's software
driver to tell it that the device is now in state D0. The sys-
tem software can clear the PME_STATUS bit either be-
fore, after, or at the same time that it puts the device
back into the D0 state.
LED
Output
Indication
Driver Mode
Open Drain -
Active Low
Open Drain -
Active Low
Open Drain -
Active Low
Open Drain -
Active Low
Open Drain -
Active Low
Pulse Stretch
LED0
Link Status
Enabled
LED1
Receive
Status
Enabled
LED2
Power
Enabled
LED3
Transmit
Status
Enabled
LED4
Speed
Enabled
COL
COLE
FDLS
FDLSE
LNKS
LNKSE
RCV
RCVE
RCVM
RCVME
XMT
XMTE
To
Pulse
MR_SPEED_SEL
100E
MPS
MPSE
POWER
POWERE
22399A-49
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