
124
Am79C978A
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR15: Mode
This register
’
s fields are loaded during the Am79C978A
controller initialization routine with the corresponding
Initialization Block values, or when a direct register write
has been performed on this register.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
PROM
Promiscuous
PROM = 1, all incoming receive
frames are accepted.
Mode.
When
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
14
DRCVBC
Disable
When
Am79C978A controller from re-
ceiving broadcast messages.
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of
H_RESET
(broadcast messages will be re-
ceived) and is unaffected by
STOP.
Receive
set,
Broadcast.
disables
the
or
S_RESET
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
13
DRCVPA
Disable Receive Physical Ad-
dress. When set, the physical
address detection (Station or
node ID) of the Am79C978A
controller
will
Frames addressed to the nodes
individual physical address will
not be recognized.
be
disabled.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
12-9
RES
Reserved locations. Written as
zeros and read as undefined.
8-7 PORTSEL[1:0] Port Select bits allow for soft-
ware controlled selection of the
network medium. The only legal
values for this field is 11.
This bit is read/write accessible only when ei-
ther the STOP or the SPND bit is
set. Cleared by H_RESET or
S_RESET and is unaffected by
STOP.
6
INTL
Internal Loopback. See the de-
scription of LOOP (CSR15, bit 2).
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
5
DRTY
Disable Retry. When DRTY is set
to 1, the Am79C978A controller
will attempt only one transmission.
In this mode, the device will not
protect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because auto-
matic retransmission will not be
necessary. When DRTY is set to
0, the Am79C978A controller will
attempt 16 transmissions before
signaling a retry error.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
4
FCOLL
Force Collision. This bit allows
the collision logic to be tested.
The Am79C978A controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop-
back
transmission
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
attempts,
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
3
DXMTFCS
Disable Transmit CRC (FCS).
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
the
transmitted
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in TMD1.
frame.