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參數(shù)資料
| 型號： | AM79C978AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 74/256頁 |
| 文件大小： | 3505K |
| 代理商： | AM79C978AKCW |
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Am79C978A
DETAILED FUNCTIONS
1 Mbps HomePNA PHY
The integrated HomePNA transceiver is a physical
layer device supporting the HomePNA specification 1.1
for home phone line networking. It provides all of the
PHY layer functions required to support 1 Mbps data
transfer speeds over common residential phone wiring.
All data bits are encoded into the relative time position
of a pulse with respect to the previous one, the wave-
form on the wire consists of a 7.5 MHz carrier sinusoid
enclosed within an exponential (bell shaped) enve-
lope. The waveform is produced by generating four
7.5 MHz square wave cycles and passing them
through a bandpass filter.
The HomePNA PHY frame consists of a HomePNA
header that replaces the normal Ethernet 64-bit pream-
ble and delimiter and is prepended to a standard Ether-
net packet starting with the source address and ending
with the CRC.
Only the PHY layer and its parameters are modified
from that of the standard Ethernet implementation. The
HomePNA PHY layer is designed to operate with a
standard Ethernet MAC layer controller implementing
all the CSMA/CD protocol features.
The frame begins with a characteristic SYNC interval
that delineates the beginning of a HomePNA frame fol-
lowed by an Access ID (AID) which encodes 8 bits of
Access ID and 4 bits of control word. The Access ID is
used to detect collisions and is dynamically assigned,
while the control word carries speed and power infor-
mation.
The AID is followed by a silence interval, then 32 bits of
data reserved for PHY layer communication. These
bits are accessible via HPR20 and HPR21 and are for
future use.
The data encoding consists of two symbol types: an
AID symbol and a data symbol. The AID symbol is al-
ways transmitted at the same speed and encodes two
bits that determine the pulse position (one of four) rel-
ative to the previous pulse. The access symbol interval
is fixed.
The data symbol interval is variable. The arriving bit
stream is blocked into from 3 to 6 bit blocks according
to a proprietary (RLL25
) algorithm. The bits in each
block are then used to encode a data symbol. Each
symbol consists of a Data Inter Symbol Blanking Inter-
val (DISBI) and then a pulse at one of 25 possible po-
sitions. The bits in the data block determine the pulse
position. Immediately after the pulse a new symbol in-
terval begins. During the DISBI the receiver ignores all
incoming pulses to allow network reflections to die out.
Any station may be programmed to assume the role of
a PHY master and remotely command, via the control
word, the rest of the units on the network to change
their transmit speed or power level.
Many of the framing parameters are programmable in
the HomePNA PHY and will allow future modifications to
both transmission speed as well as noise and reflection
rejection algorithms.
Two default speeds are provided, low at 0.7 Mbps and
high at 1 Mbps. The center frequency is also program-
mable for future use.
HomePNA PHY Medium Interface
Framing
The HomePNA frame on the phone wire network con-
sists of a header generated in the PHY prepended to
an IEEE 802.3 Ethernet data packet received from the
MAC layer. See Figure 38.
When transmitting on the phone wire pair, the
HomePNA PHY first receives an Ethernet MAC frame
from the MAC. The 8 octets of preamble and delimiter
are stripped off and replaced with the HomePNA PHY
header described below, then transmitted on the phone
wire network.
During a receive operation, the reverse process is exe-
cuted. When a HomePNA frame is received by the
PHY, the header is stripped off and replaced with the
four octets of preamble and delimiter of the IEEE 802.3
Ethernet MAC frame specification and then passed on
to the MAC layer.
相關PDF資料 |
PDF描述 |
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| AM79C978AVCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
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