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參數(shù)資料
| 型號(hào)： | AK61584 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| 中文描述： | 雙低功耗的T1/E1線路接口 |
| 文件頁(yè)數(shù)： | 6/38頁(yè) |
| 文件大?。?/td> | 364K |
| 代理商： | AK61584 |
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ASAHI KASEI
[AK61584]
0185-E-00 98/04
SWITCHING CHARACTERISTICS-T1 CLOCK/DATA
(T
A
= -40 to 85
o
C;power supply
pins within +/-5% of nominal; Inputs: Logic 0=0V, logic 1=DV+)(See Figures 1,2, and 3)
Parameter
TCLK Frequency (Note 25)
TCLK Duty Cycle
RCLK Duty Cycle (Note 26)
Rise Time All Digital Outputs (Note 27)
Fall Time All Digital Outputs (Note 27)
TPOS/TNEG to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG Hold Time
RPOS/RNEG to RCLK Rising Setup Time
RCLK Rising to RPOS/RNEG Hold Time
Notes:
25. Max value of 8.192 MHz describes the maximum burst rate of a gapped input clock(TCLK).
For the gapped clock to be tolerated by the AK61584, the jitter attenuator must be switched to
transmit path of the line interface. The maximum gap size is defined in the Analog Specification table.
26. RCLK duty cycle may be outside the spec limits when jitter attenuator is in the receive path,
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50pF.
Symbol
f
tclk
t
pwh2
/t
pw2
t
pwh1
/t
pw1
t
r
t
r
t
su2
t
h2
t
su1
t
h1
Min
-
30
45
-
-
25
25
-
-
Typ
1.544
50
50
-
-
-
-
274
274
Max
-
70
55
65
65
-
-
-
-
Units
MHz
%
%
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS-E1 CLOCK/DATA
(T
A
= -40 to 85
o
C;power supply
pins within +/-5% of nominal; Inputs: Logic 0=0V, Logic 1=DV+)(See Figures 1, 2, and 3)
Parameter
TCLK Frequency (Note 25)
TCLK Duty Cycle
RCLK Duty Cycle (Note 26)
Rise Time All Digital Outputs (Note 27)
Fall Time All Digital Outputs (Note 27)
TOPS/TNEG to TCLK Falling Setup Time
TCLK Falling to TOPS/TNEG Hold Time
RPOS/RNEG to RCLK Rising Setup Time
RCLK Rising to RPOS/RNEG Hold Time
Symbol
f
tclk
t
pwh2
/t
pw2
t
pwh
1/t
pw1
t
r
t
r
t
su2
t
h2
t
su1
t
h1
Min
-
30
45
-
-
25
25
-
-
Typ
2.048
50
50
-
-
-
-
194
194
Max
-
70
55
65
65
-
-
-
-
Units
MHz
%
%
ns
ns
ns
ns
ns
ns
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| AK616-.5 | 功能描述:CABLE AUDIO CD-ROM 3-FOLD .5M RoHS:否 類別:電纜組件 >> 矩形 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 連接器類型:插頭至插頭 位置數(shù):30 行數(shù):2 間距 - 連接器:0.100"（2.54mm） 間距 - 線纜:0.050"（1.27mm） 長(zhǎng)度:1.50'（457.20mm） 特點(diǎn):電極標(biāo)記 顏色:多色，帶狀 屏蔽:無(wú)屏蔽 使用:- 電纜端接:IDC 觸點(diǎn)表面涂層:金 觸點(diǎn)涂層厚度:30µin（0.76µm） |
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| AK6161024W | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:65,536 x 32 Bit CMOS/BiCMOS Static Random Access Memory |
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