參數(shù)資料
型號(hào)： AK61584
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No
中文描述： 雙低功耗的T1/E1線路接口
文件頁(yè)數(shù)： 37/38頁(yè)
文件大?。?/td> 364K
代理商： AK61584
ASAHI KASEI
[AK61584]
0185-E-00
98/04
-37-
T1/E1 Data Inputs And Outputs
RCLK1, RCLK2 -Receive Clock, Pins 1, 48.
RPOS1/RDATA1, RPOS2/RDATA2 -Receive Positive Data, Pins 2, 47.
RNEG1, RNEG2 -Receive Negative Data, -Pins 3, 46.
The receiver recovered clock and NRZ digital data is output on these pins. CLKE determines the clock
edge for which RPOS and RNEG are stable and valid. See Table 3.
A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1
on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. In
coder mode, the decoded digital data stream is output on RDATA.
RTIP1, RRING1, RTIP2, RRING2 -Receive Tip, Receive Ring, Pins 17, 18, 32, 31.
The AMI receive signal is input to these pins. Step-down transformer is required on these inputs.
Data and clock are recovered and output on RPOS/RNEG (RDATA) and RCLK.
TCLK1, TCLK2 -Transmit Clock, Pin 4, 45.
TPOS1/TDATA1, TPOS2/TDATA2 -Transmit Positive Data, Pins 5, 44.
TNEG1, TNEG2 -Transmit Negative Data, -Pins 6, 43.
Inputs for clock and data to be transmitted. The signal is driven on to the line through
TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes
a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be
transmitted. In coder mode, the un-encoded digital data stream is input on TDATA.
TTIP1, TRING1, TTIP2, TRING2 -Transmit Tip, Transmit Ring, Pins 11, 14, 38, 35.
The AMI signal is driven to the line through these pins. This output is designed to drive
the primary of the recommended transformer. In transparent mode, TPOS drives TTIP, and TNEG
drives TRING. In coder mode, TDATA drives TTIP and TRING.
Test
J_TCLK-JTAG Test Clock, Pin 40.
Data on pins J_TDI and J_TDO in valid on the rising edge of J_TCK. When J_TCK in stopped
low, all JTAG registers remain unchanged.
J_TMS -JTAG Test Mode Select, Pin 39.
An active high signal on this pin enables the JTAG serial port. Connected to an internal
pull-up resistor.
J_TDI -JTAG Test Data In, Pin 10.
JTAG data is shifted into the AK61584 via this pin. connected to an internal pull-up
resistor. Data should be stable on the rising edge of J_CLK.
J_TDO -JTAG Test Data Out, Pin 8.
JTAG data is shifted out of the AK61584 via this pin. This pin is active except when JTAG
testing is in progress. J_TDO will be updated on the falling edge of J_TCK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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