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參數(shù)資料
| 型號： | AK61584 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| 中文描述： | 雙低功耗的T1/E1線路接口 |
| 文件頁數(shù)： | 25/38頁 |
| 文件大小： | 364K |
| 代理商： | AK61584 |
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ASAHI KASEI
[AK61584]
0185-E-00 98/04
Boundary Scan Register: The BSR can be connected in
parallel to all the digital I-O pins, and provides the
mechanism for applying/reading test patterns to/from
the board traces. The BSR is initialized and read
using the instruction SAMPLE/PRELOAD. The bit
ordering for the BSR is the same as the top-view packaged
pin out, counter-clockwise beginning with PD1 (pin 15)
and ending with LOS1 (pin 7), as shown in Table 6. The
analog, oscillator, power, ground, ATTEN0, CLKE
and MODE pins are not included as part of the
boundary-scan register. ATTEN0, CLKE and MODE are
not included because they are typically hard-wired to
power or ground on a board.
All output pins are 3-state pins (logic high, logic low or high
impedance); their value can be set via the
PRELOAD/EXTEST instructions. Since outputs
are all 3-state, 2 bits are required to specify the states of
each output pin in the BSR.The first bit (which is shifted
in first) contains the testing data which may be output on
the pin. The second bit, which is shifted in following the
first bit, selects between an output-enabled state (bit set to
1) or high-impedance state (bit set to 0). Thus, two
J_TCK cycles are required to load testing data for
each output pin.
Each input pin requires only 1 bit in the BSR.
The bi-directional pins, TNEG1/AIS1, TNEG2/AIS2,
INT/RLOOP1,
LOS1,
LLOOP2/SDO, TAOS1/SDI, TAOS2/SPOL, and the
CON<0:2> pins have three bits in the BSR. The first
bit shifted into the BSR captures the value of the pin.
This pin may have its value set externally (if the third bit
is 0) or set internally (if the third bit is 1). The second bit
shifted into the BSR sets the output value. This value is
output on the pin when the third bit is 1. The third bit con-
figures the output driver as high-impedance (bit set to
0) or active (bit set to 1).
LOS2,
LLOOP1/SCLK,
Note that the interrupt pin on the AK61584 has the
ability of being a active high or active low signal. In
host mode, the IPOL pin controls this functionality.
During JTAG testing in host mode, the polarity of the
INT pin will be determined by the state of the IPOL pin.
The INT pin on the AK61584 should not be configured
as an output by the JTAG BSR if the device is in hard-
ware mode. Likewise, the INT pin should not be config-
ured as an input by the JTAG BSR if the device is in
host mode.
Thus, the entire BSR is 62 bits long.
BSR
bits
Name
1
PD1
2
IPOL,RLOOP2
3
PD2
4
CODER2
5-7
LOS2
8-10
TNEG2,AIS2
11
TPOS2,TDATA2
12
TCLK2
13-14 RNEG2,BPV2
15-16 RPOS2,RDATA2
17-18 RCLK2
19
CODER1
20
CON22
21-23 CON21
24-26 CON12
27-29 CON11
30-32 CON02
33-35 CON01
36-38 TAOS2
39-41 SDI,TAOS1
42-44 SDO,LLOOP1
45
SCLK,LLOOP2
46-48 INT,RLOOP1
49
CS,ATTEN1
50-51 RCLK1
52-53 RPOS1,RDATA1
54-55 RNEG1,BPV1
56
TCLK1
57
TPOS1,TDATA1
58-60 TNEG1,AIS1
61-63 LOS1
Table 6 Boundary Scan Register Contents
Pin
PIN
#
15
33
34
41
42
43
44
45
46
47
48
49
50
51
52
53
54
58
59
60
61
62
63
64
1
2
3
4
5
6
7
Pad
Type
input
input
input
input
bi-directional
bi-directional
input
input
output
output
output
input
input
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
input
bi-directional
input
output
output
output
input
input
bi-directional
bi-directional
Bypass Register: The Bypass register consists of a single
bit, and provides a serial path between J_TDI and J_TDO,
bypassing the BSR. The provision of this register allows
the bypassing of those segments of the board-level serial
test register which are not required for a specific test. This
also reduces test access times, by reducing the total num-
ber of shifts required from J_TDI to J_TDO.
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