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參數(shù)資料
| 型號： | AK61584 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| 中文描述： | 雙低功耗的T1/E1線路接口 |
| 文件頁數(shù)： | 19/38頁 |
| 文件大?。?/td> | 364K |
| 代理商： | AK61584 |
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ASAHI KASEI
[AK61584]
0185-E-00
98/04
-19-
REGISTERS
The control and status registers are defined in Table 5,
and are accessible in host mode. Each channel has its
own set of Status, Mask and Control. The status register
is read-only. Writing to the status register has no impact on
its contents. Interrupts are generated on the INT pin every
time a status register changes. Reading a status register
resets all bits in that status register to 0. The mask reg-
ister allows the user to mask interrupts on a status
register on a per-bit basis. The control registers select fea-
tures /functionality.
Status Registers Description
Each bit in the status register is defined below.
AIS and Latched-AIS: Indicates an all-ones condition.
AIS is set high while AIS condition is currently de-
tected. Latched-AIS indicates that a AIS condition has
occurred since the last read of the status register.
Interrupt: Indicates that the status register has changed
sometime since the last read of the status register.
L
atched-BPV: indicates a bipolar violation event has
been detected in the receiver sometime since the last
read of the status register. This bit is set only when the
line-code decoder is enabled.
Latched-Overflow: Indicates that a waveform generated
using the Arbitrary Waveforms has exceeded full scale
sometime since the last read of the status register.
(Optional information, refer to the Application Note.)
LOS and Latched-LOS : Indicates loss of signal
condition. LOS is set high while LOS condition is
currently detected. Latched-LOS indicates that a
LOS condition has occurred since the last read of
the status register.
Latched-reset: Indicates that a reset event
(power-up or manual) has occurred since the last read
of the status register. This status bit is not maskable.
Definition
Reset
Value
Register
Address
h10
b0000
Bit Name
1
0
Channel 1 Status
7
6
5
4
3
2
1
0
LOS1
Latched-LOS1
AIS1
Latched-AIS1
Latched-BPV1
Latched
-Overflow1
Latched-reset
Interrupt1
LOS currently detected
LOS event since last read
AIS currently detected
AIS event since last read
BPV event since last read
Pulse overflow since last
Read
Reset event since last read
Interrupt event since last
Read
no LOS
no LOS
no AIS
no AIS
no BPV
no overflow
no reset
no interrupt
1
1
0
0
0
0
1
0
h11
b0001
Channel 2 Status
7
6
5
4
3
2
1
0
LOS2
Latched-LOS2
AIS2
Latched-AIS2
Latched-BPV2
Latched
-Overflow2
reserved
Interrupt2
LOS currently detected
LOS event since last read
AIS currently detected
AIS event since last read
BPV event since last read
Pulse overflow since last
Read
Interrupt event since last
Read
Table 5(a). Status Registers
no LOS
no LOS
no AIS
no AIS
no BPV
no overflow
no interrupt
1
1
0
0
0
0
0
0
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