參數(shù)資料
型號(hào)： AK61584
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No
中文描述： 雙低功耗的T1/E1線路接口
文件頁(yè)數(shù)： 27/38頁(yè)
文件大小： 364K
代理商： AK61584
ASAHI KASEI
[AK61584]
0185-E-00 98/04
Test-Logic-Reset State
In this state, the test logic is disabled so that normal opera-
tion of the device can continue unhindered. During
initialization, the AK61584 initializes the instruction
register.
No matter what the original state of the controller,
the controller enters Test-Logic-Reset state when the
J_TMS input is held high (logic 1) for at least five
rising edges of J_TCK. The controller remains in this
state while J_TMS is high. The AK61584 proces-
sor automatically enters this state at power-up.
Run-Test/Idle State
This is a controller state between scan operations. Once
in this state, the controller remains in this state as long as
J_TMS is held low. The instruction register and all test
data registers retain their previous state. When J_TMS is
high and a rising edge is applied to J_TCK, the
controller moves to the Select-DR state.
Select-DR-Scan State
This is a temporary controller state. The test data register
selected by the current instruction retains its previous state. If
J_TMS is held low and a rising edge is applied to
J_TCK when in this state, the controller moves into the
Capture-DR state, and a scan sequence for the selected
test data register is initiated. If J_TMS is held high
and a rising edge applied to J_TCK, the controller moves
to the Select-IR-Scan state.
The instruction does not change in this state.
Capture-DR State
In this state, the Boundary Scan Register captures input
pin data if the current instruction is EXTEST or
SAMPLE/PREROAD. The other test data registers,
which to not have parallel input, are not changed.
The instruction does not change in this state.
When the TAP controller is in this state and a rising
edge is applied to J_TCK, the controller enters the
Exit1-DR state if J_TMS is high or the Shift-DR state if
J_TMS is low.
Figure 17. TAP controller State Diagram
Select-DR-Scan
0
Capture-DR
0
Shift-DR
1
Exit1-DR
0
Pause-DR
1
Exit2-DR
1
Update-DR
Test-Logic-Reset
Run-Test/Idle
Select-IR-Scan
Capture-IR
0
Shift-IR
1
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
0
1
1
0
1
1
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
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